psub Guard ring design and modeling for the purpose of substrate noise isolation in the SOC era

IEEE Electron Device Letters

Volumn 26, Issue 9, 2005, Pages 693-695

  Hsu, Tsun Lai ^a   Chen, Yu Chia ^a   Tseng, Hua Chou ^a   Liang, Victor ^a   Jan, Jin Shyong ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Lump circuit model; n well guard ring; p minus substrate guard ring; p plus guard ring (psub GR); Substrate noise isolation

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

EQUIVALENT LUMP CIRCUIT MODEL; GUARD RING DESIGN; GUARD RING MODELING; P-MINUS SUBSTRATE GUARD RING; SUBSTRATE NOISE ISOLATION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 26444580188     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.854351     Document Type: Article

References (6)

1. H. Darabi, S. Khorram, and H.-M. Chien, "A 2.4-GHz CMOS transceiver for bluetooth," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 2016-2024, Dec. 2001.
2. M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, "Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 473-485, Mar. 2001.
3. K. Joardar, "Comparison of SOI and junction isolation for substrate crosstalk suppression in mixed mode integrated circuits," IEEE Electron Device Lett., vol. 31, no. 12, pp. 1230-1231, Dec. 1995.
4. K. Benaissa, J.-Y. Yang, D. Crenshaw, B. Williams, S. Sridhar, J. Ai, G. Boselli, S. Zhao, S. Tang, S. Ashburn, P. Madhani, T. Blythe, N. Mahalingam, and H. S. Shichijo, "RF CMOS on high-resistivity substrates for system-on-chip applications,"IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 567-576, Mar. 2003. h.S. Shichijo
5. W.-K. Yeh, S.-M. Chen, and Y.-K. Fang, "Substrate noise-coupling characterization and efficient suppression in CMOS technology," IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 817-819, May 2004.
6. R. R. Troutman, Latchup in CMOS Technology. Boston, MA: Kluwer, 1986, pp. 165-165.