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Volumn 3562, Issue PART II, 2005, Pages 395-404

Reconfigurable hardware implementation of neural networks for humanoid locomotion

Author keywords

[No Author keywords available]

Indexed keywords

DATA ACQUISITION; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; TRANSFER FUNCTIONS;

EID: 26444553364     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11499305_41     Document Type: Conference Paper
Times cited : (8)

References (12)
  • 3
    • 0242276280 scopus 로고    scopus 로고
    • Inverse kinematics for humanoid robots using artificial neural networks
    • R. Moreno-Díaz, F.R. Pichler (eds.) Computer Aided Systems Theory - EUROCAST-2003. Springer-Verlag, Berlin
    • De Lope, J., González-Careaga, R., Zarraonandia, T., Maravall, D. (2003) Inverse kinematics for humanoid robots using artificial neural networks. In R. Moreno-Díaz, F.R. Pichler (eds.) Computer Aided Systems Theory - EUROCAST-2003, LNCS 2809. Springer-Verlag, Berlin, 448-459
    • (2003) LNCS , vol.2809 , pp. 448-459
    • De Lope, J.1    González-Careaga, R.2    Zarraonandia, T.3    Maravall, D.4
  • 4
    • 26444530934 scopus 로고    scopus 로고
    • Solving the inverse kinematics in humanoid robots: A neural approach
    • J. Mira, J.R. Álvarez (eds.) Artificial Neural Nets Problem Solving Methods. Springer-Verlag, Berlin
    • De Lope, J., Zarraonandia, T., González-Careaga, R., Maravall, D. (2003) Solving the inverse kinematics in humanoid robots: A neural approach. In J. Mira, J.R. Álvarez (eds.) Artificial Neural Nets Problem Solving Methods, LNCS 2687. Springer-Verlag, Berlin, 177-184
    • (2003) LNCS , vol.2687 , pp. 177-184
    • De Lope, J.1    Zarraonandia, T.2    González-Careaga, R.3    Maravall, D.4
  • 5
    • 0026838206 scopus 로고
    • Ganglion - A fast field-programmable gate array implementation of a connectionist classifier
    • Cox, C.E., Blanz, E. (1992) Ganglion - A fast field-programmable gate array implementation of a connectionist classifier. IEEE J. of Solid-State Circuits, 28, 288-299
    • (1992) IEEE J. of Solid-state Circuits , vol.28 , pp. 288-299
    • Cox, C.E.1    Blanz, E.2
  • 7
    • 0028752759 scopus 로고
    • RRANN: A hardware implementation of the back-propagation algorithm using reconfigurable FPGAs
    • Eldredge, J.G., Hutchings, B.L. (1994) RRANN: A hardware implementation of the back-propagation algorithm using reconfigurable FPGAs. Proc. of IEEE Int. Conf. on Neural Networks, 2097-2102
    • (1994) Proc. of IEEE Int. Conf. on Neural Networks , pp. 2097-2102
    • Eldredge, J.G.1    Hutchings, B.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.