An enhanced cut-points algorithm in formal equivalence verification

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 171-176

  Khasidashvili, Zurab ^a   Moondanos, John ^a   Kaiss, Daher ^a   Hanna, Ziyad ^a  

^a INTEL CORPORATION   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS;

CUT POINT; FALSE NEGATIVES; FORMAL EQUIVALENCE VERIFICATION; INPUT VARIABLES; PENTIUM; RE CONVERGENCES; VERIFICATION ALGORITHMS;

MICROPROCESSOR CHIPS;

EID: 26444446170     PISSN: 15526674     EISSN: None     Source Type: Journal    
DOI: 10.1109/HLDVT.2001.972825     Document Type: Article

References (8)

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3. J. Moondanos, C. Seger, Z. Hanna, D. Kaiss: Divide and Conquer Combinational Logic Equivalence Verification with False Negative Elimination, CAV 2001, Springer LNCS, vol. 2102, pp. 131-143.
4. R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J.A. Abraham, D.S. Fussell: An efficient filter-based approach for combinational verification. IEEE Transactions on CAD, vol. 18, num. 11, 1999.
5. S. M. Reddy, W. Kunz, and D. K. Pradhan: Novel verification framework combining structural and OBDD methods in a synthesis environment, DAC 1995, pp. 414-419.
6. T. Nakaoka, S. Wakabayashi, T. Koide, and N. Yoshida: A Verification Algorithm for Logic Circuits with Internal Variables, ISCAS 1995, pp. 1920-1923.
7. A. Kuhlmann and F. Krohm: Equivalence Checking using Cuts and Heaps, DAC 1997.
8. Pixley, et al. Method for determining functional equivalence between design models United States Patent 5754454, May 19, 1998.