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Volumn 2451, Issue , 2002, Pages 188-197

A new methodology for efficient synchronization of RNS-based VLSI systems

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; SYNCHRONIZATION; VLSI CIRCUITS;

EID: 25744455994     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45716-x_19     Document Type: Conference Paper
Times cited : (4)

References (15)
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  • 2
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    • J. Yoo, G. Gopalakrishnan and K. F. Smith, “Timing Constraints for High-speed Counterflow-clocked Pipelining”, IEEE Transactions on VLSI Systems, vol. 7, no. 2, pp. 167–173, Jun. 1999.
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  • 5
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    • (2001) Journal of VLSI Signal Processing , vol.28 , Issue.1-2 , pp. 115-128
    • Meyer-Bäse, U.1    Garcia, A.2    Taylor, F.J.3
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    • D. F. Wann and N. A. Franklin, “Asynchronous and Clocked Control Structures for VLSI Based Interconnect Networks”, IEEE Transactions on Computers, vol 32, no.5, pp. 284–293, May 1983.
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  • 12
    • 33747530935 scopus 로고    scopus 로고
    • Clock Distribution Networks in Synchronous Digital Integrated Circuits
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.