Implementation of a communications using FPGAs and RNS arithmetic

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 28, Issue 1-2, 2001, Pages 115-128

  Meyer Bäse, Uwe ^a   García, Antonio ^b   Taylor, Fred ^c  

^a FAMU FSU COLLEGE OF ENGINEERING   (United States)

^b UNIVERSIDAD AUTÓNOMA DE MADRID   (Spain)

^c UNIVERSITY OF FLORIDA   (United States)

Author keywords

Channelizer; Complex programmable logic devices (CPLD); Digital signal processing (DSP); Field programmable gate array (FPGA); Field programmable logic (FPL); Residue number system (RNS); Zero IF filter

Indexed keywords

DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; LOGIC DEVICES; MICROPROCESSOR CHIPS;

COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD); RESIDUE NUMBER SYSTEM (RNS);

DIGITAL SIGNAL PROCESSING;

EID: 0035341947     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008167323437     Document Type: Article

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