Timing constraints for high-speed counterflow-clocked pipelining

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 2, 1999, Pages 167-173

  Yoo, Jae Tack ^a,b   Gopalakrishnan, Ganesh ^a,c   Smith, Kent F ^c  

^a IEEE

^b Anyang University   (South Korea)

^c UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS;

CLOCK SKEW; CLOCK TIMING CONSTRAINTS; HIGH-SPEED COUNTERFLOW-CLOCKED PIPELINING;

VLSI CIRCUITS;

EID: 0032665835     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.766743     Document Type: Article

References (19)

1. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990, pp. 353-355.
2. D. W. Dobberpuhl et al., "A 200-MHz 64-b dual-issue CMOS microprocessor," IEEE J. Solid-State Circuits, vol. 27, pp. 1555-1569, Nov. 1992.
3. S. Yinger et al., "HBT gate array for 5 GHz ASIC's," in 15th Annu. GaAs IC Symp. Tech. Dig., Oct. 1993.
4. S. Dutta and W. Wolf, "Asymptotic limits of video signal processing architectures," presented at the ICCD, 1994.
5. D. Conner, "Submicron technologies require floorplanning," prsented at the EDA, Sept. 1993.
6. J. Yuan and C. Svensson, "Pushing the limits of standard CMOS," IEEE Spectrum Mag., vol. 28, pp. 52-53, Feb. 1991.
7. A. L. Fisher and H. T. Kung, "Synchronizing large VLSI processor array," IEEE Trans. Comput., vol. C-34, pp. 1734-1740, Aug. 1985.
8. W. J. Bowhill et al., "Circuit implementation of a 300-MHz 64-bit second-generation CMOS alpha chip," Digital Tech. J., vol. 7, no. 1, 1995.
9. K. A. Sakallah et al., "Synchronization of pipelines," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1132-1146, Aug. 1993.
10. I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, no. 6, pp. 720-738, June 1989.
11. A. J. Martin, "Tomorrow's digital hardware will be asynchronous and verified," California Inst. Technol., Pasadena, CA, Tech. Rep. CS-TR-93-26, 1993.
12. D. Fan et al., "A CMOS parallel adder using wave pipelining," in Proc. Advanced Res. VLSI and Parallel Syst. Brown/MIT Conf., 1992.
13. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, 2nd Ed. Reading, MA: Addison-Wesley, 1993, p. 239.
14. A. El-Amawy, "Clocking arbitrarily large computing structure under constant skew bound," IEEE Trans. Parallel Distrib. Syst., vol. 4, pp. 241-255, Mar. 1993.
15. J. Yoo et al., "High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips," in Proc. 16th Conf. Advanced Res. VLSI, 1995.
16. B. M. Pangrle and D. D. Gajski, "Design tools for intelligent silicon compilation," IEEE Trans. Computer-Aided Design, vol. CAD-6, Nov. 1987.
17. J. Yoo, "High-speed counterflow-clocked pipelining illustrated on the design of subband vector quantizer chips," Ph.D. dissertation, Dept. Comput. Sci., Univ. Utah, Salt Lake City, Dec. 1995.
18. M. Winzker et al., "VLSI chip set for 2-D HDTV subband filtering with on-chip line memories," IEEE J. Solid-State Circuits, vol. 28, pp. 1354-1361, Dec. 1993.
19. P. P. Vaidyanathan, Multirate Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993.