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Volumn 5756, Issue , 2005, Pages 1-12

Integrating DfM components into a cohesive design-to-silicon solution

Author keywords

Critical area analysis (CAA); Design for manufacturability (DfM); Glyph based layout; Physical design characterization (PDC); Resolution enhancement techniques (RET); Restricted design rules (RDR)

Indexed keywords

LITHOGRAPHY; OPTIMIZATION; PRODUCT DESIGN;

EID: 25144433780     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.604723     Document Type: Conference Paper
Times cited : (18)

References (9)
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    • ITRS, //www.itrs.net/Common/2004Update/2004Update.htm
  • 2
    • 25144500881 scopus 로고    scopus 로고
    • What do we see: How ten start-ups, four EDAs, equipment and mask vendors, foundries, and IDMs are shaping IC DFM infrastructure
    • Design and Process Integration for Microelectronic Manufacturing III
    • Jim Hogan et al., "What do we see: how ten start-ups, four EDAs, equipment and mask vendors, foundries, and IDMs are shaping IC DFM infrastructure," Design and Process Integration for Microelectronic Manufacturing III, SPIE 5379, 2004
    • (2004) SPIE , vol.5379
    • Hogan, J.1
  • 3
    • 2942666050 scopus 로고    scopus 로고
    • High-performance circuit design for the RET-enabled 65-nm technology node
    • Design and Process Integration for Microelectronic Manufacturing III
    • Lars Liebmann et al., " High-performance circuit design for the RET-enabled 65-nm technology node," Design and Process Integration for Microelectronic Manufacturing III, SPIE 5379, 2004
    • (2004) SPIE , vol.5379
    • Liebmann, L.1
  • 4
    • 0023166026 scopus 로고
    • Design for the life cycle
    • (Virginia Polytechnic Inst & State Univ, Blacksburg, VA, USA) Jan
    • Fabrycky, Wolter J. "Design For The Life Cycle," (Virginia Polytechnic Inst & State Univ, Blacksburg, VA, USA) Source: Mechanical Engineering, v 109, n 1, Jan, 1987, p 72-74
    • (1987) Source: Mechanical Engineering , vol.109 , Issue.1 , pp. 72-74
    • Fabrycky, W.J.1
  • 6
    • 0021466353 scopus 로고
    • Modeling of defects in integrated circuit photolithographic patterns
    • July
    • C.H. Stapper, "Modeling of defects in integrated circuit photolithographic patterns", IBM Journal of Research and Development, Volume 28, Number 4, July, 1984.
    • (1984) IBM Journal of Research and Development , vol.28 , Issue.4
    • Stapper, C.H.1
  • 8
    • 0030651820 scopus 로고    scopus 로고
    • A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
    • Fook-Luen Heng, Zhan Chen, Gustavo Tellez, "A VLSI Artwork Legalization Technique Based on a New Criterion of Minimum Layout Perturbation", International Symposium on Physical Design, 1997, pp 116-121
    • (1997) International Symposium on Physical Design , pp. 116-121
    • Heng, F.-L.1    Chen, Z.2    Tellez, G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.