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Volumn 3440, Issue , 2005, Pages 382-396

Dynamic symmetry reduction

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; FORMAL LOGIC; ITERATIVE METHODS; MATHEMATICAL MODELS; PROBLEM SOLVING;

EID: 24644503714     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-540-31980-1_25     Document Type: Conference Paper
Times cited : (40)

References (19)
  • 1
    • 24644500695 scopus 로고    scopus 로고
    • Combining symmetry reduction and under-approximation for symbolic model checking
    • [BG02]
    • [BG02] Sharon Barner and Orna Grumberg. Combining symmetry reduction and under-approximation for symbolic model checking. Computer-Aided Verification (CAV), 2002.
    • (2002) Computer-aided Verification (CAV)
    • Barner, S.1    Grumberg, O.2
  • 2
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • [Bry86]
    • [Bry86] Randy E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 1986.
    • (1986) IEEE Transactions on Computers
    • Bryant, R.E.1
  • 3
    • 85050550846 scopus 로고
    • Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints
    • [CC77]
    • [CC77] Patrick Cousot and Radhia Cousot. Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints. Principles of Programming Languages (POPL), 1977.
    • (1977) Principles of Programming Languages (POPL)
    • Cousot, P.1    Cousot, R.2
  • 4
    • 0002367651 scopus 로고
    • The design and synthesis of synchronization skeletons using temporal logic
    • [CE81]
    • [CE81] Edmund M. Clarke and E. Allen Emerson. The design and synthesis of synchronization skeletons using temporal logic. Logic of Programs (LOP), 1981.
    • (1981) Logic of Programs (LOP)
    • Clarke, E.M.1    Emerson, E.A.2
  • 15
    • 0032641334 scopus 로고    scopus 로고
    • Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
    • [PB99]
    • [PB99] Manish Pandey and Randal E. Bryant. Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation. IEEE Transactions on Computer-Aided Design, 1999.
    • (1999) IEEE Transactions on Computer-aided Design
    • Pandey, M.1    Bryant, R.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.