Technology requirements for chip-on-chip packaging solutions

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 802-808

  Topper M ^a   Fritzsch, Th ^a   Glaw, V ^a   Jordan, R ^a   Lopper, Ch ^a   Roder J ^a   Dietrich, L ^a   Lutz, M ^a   Oppermann, H ^a   Ehrmann, O ^a   Reichl, Herbert ^a  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

3 D Packaging; Chip on Chip Packaging; System in Package (SiP); Wafer Level Packaging

Indexed keywords

ELECTRIC WIRING; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; MICROELECTRONICS; SILICON WAFERS; THICKNESS MEASUREMENT;

3-D PACKAGING; SYSTEM IN PACKAGE; WAFER LEVEL PACKAGING;

MICROPROCESSOR CHIPS;

EID: 24644495781     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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