Fault testing for reversible circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 410-416

  Patel, K N ^a   Hayes, J P ^a   Markov, I L ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Circuit faults; Circuit testing; Electrical fault detection; Energy consumption; Energy dissipation; Government; Logic circuits; Logic gates; Quantum computing; Very large scale integration

Indexed keywords

COMPUTATION THEORY; ELECTRIC FAULT LOCATION; ENERGY DISSIPATION; ENERGY UTILIZATION; FAULT DETECTION; INDUCTIVE LOGIC PROGRAMMING (ILP); INTEGER PROGRAMMING; INTEGRATION TESTING; LOGIC GATES; QUANTUM COMPUTERS; QUANTUM THEORY; SOFTWARE TESTING; TESTING; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; ELECTRICAL FAULT DETECTIONS; GOVERNMENT; QUANTUM COMPUTING;

LOGIC CIRCUITS;

EID: 79951613387     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197682     Document Type: Conference Paper

References (17)

1. V. D. Agrawal. An information theoretic approach to digital fault testing. IEEE Trans. on Comp., pp. 582-587, Aug. 1981.
2. C. H. Bennett. Logical reversibility of computation. IBM J. of Research and Development, pp. 525-532, Nov. 1973.
3. J. C. Bertrand, N. Giambiasi, and J. J. Mercier. Sur la recherche de l'inverse d'un automate. RAIRO, pp. 64-87, Apr. 1974.
4. J. C. Bertrand, J. J. Mercier, and N. Giambiasi. Sur la recherche de l'inverse d'un circuit combinatoire. RAIRO, pp. 21-44, Jul. 1974.
5. M. L. Bushnell and V. D. Agrawal. Essentials of Electronic Testing for Digital Memory & Mixed-Signal VLSI Circuits. Kluwer Academic Publishers, Boston, 2000.
6. J.-S. Chang and C.-S. Lin. Test set compaction for combinational circuits. IEEE Trans. on CAD, pp. 1370-1378, Nov. 1995.
7. P. F. Flores, H. C. Neto, and J. P. Marques-Silva. On applying set covering models to test set compaction. Proc. GLS-VLSI, pp. 8-11, Mar. 1999.
8. E. Fredkin and T. Toffoli. Conservative logic. Intl. J. of Theoretical Physics, vol. 21, pp. 219-253, 1982.
9. M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman and Company, New York, 1979.
10. P. Goel and B. C. Rosales. Test generation & dynamic compaction of test. Dig. Papers Intl. Test Conf., pp. 189-192, Oct. 1979.
11. D. S. Hochbaum. An optimal test compression procedure for combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, pp. 1294-1299, Oct. 1996.
12. ILOG CPLEX. http://www.ilog.com/products/cplex.
13. W. H. Kautz. Testing for faults in cellular logic arrays. Annual Symp. on Switching and Automata Theory, pp. 161-174, 1967.
14. R. Landauer. Irreversibility and heat generation in the computing process. IBM J. of Research and Development, pp. 183-191, Jul. 1961.
15. M. A. Nielsen and I. L. Chuang. Quantum Computation and Quantum Information. Cambridge University Press, 2000.
16. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes. Reversible logic circuit synthesis. Proc. IEEE/ACM Intl. Conf. on CAD, pp. 353-360, Nov. 2002.
17. P. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Combinational test generation using satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems, pp. 1167-1176, Sept. 1996.