A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 288-291

  Min, Kyeong Sik ^a   Kim, Young Hee ^b   Kim, Daejeong ^a   Kim, Dong Myeong ^a   Ahn, Jin Hong ^c  

^a Kookmin University   (South Korea)

^b Changwon National University   (South Korea)

^c Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FLASH MEMORY; LOGIC GATES; TIMING CIRCUITS;

ACTIVATION SPEED; HIGH PUMPING EFFICIENCY; OVERLAPPING CLOCKS; POSITIVE PUMP;

ELECTRIC GENERATORS;

EID: 2442614080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. T. B. Cho and P. R. Gray, "A 10-bit, 20 MS/s, 35 mW pipeline A/D converter," in IEEE Custom Integrated Circuit Conference, 1994, pp. 499-502
2. P. Favrat, P. Deval, and M. Declercq, "A high-efficiency CMOS voltage doubler," IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 410-416, March 1998.
3. Y. Kim, J. Nam, S. Lee, H. Park, J. Choi, C. Park, S. Ahn, and J. Chung, "Two-phase boosted voltage generator for low-voltage giga-bit DRAMs," IEICE Trans. Electron., vol. E83-C, no. 2, pp. 266-269, Feb. 2000.
4. K. Min and J. Chung, "A fast pump-down VBB generator for sub-1.5-V DRAMs,", IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1154-1157, July 2001.