Predictable design of low power systems by pre-implementation estimation and optimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 12-17

  Nebel, Wolfgang ^a  

^a UNIVERSITY OF OLDENBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR PHONES; ESTIMATION TOOL; LOW POWER SYSTEMS;

ALGORITHMS; BANDWIDTH; ELECTRIC POWER SYSTEMS; ESTIMATION; MICROPROCESSOR CHIPS; OPTIMIZATION; SEMICONDUCTOR MATERIALS; SYSTEMS ANALYSIS;

MICROELECTRONICS;

EID: 2442534119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. Jones, H., H., "Analysis of the Relationship between EDA Expenditures and Competitive Positioning of IC Vendors," IDS, 2002.
2. Smith, G., "ASIC Design Times Spiral out of Control", Gartner Dataquest, 2002.
3. Sarker, B., Nebel, W., and Schulte, M., Low Power Optimization Techniques in Overlap Add Algorithmus, in Proc. Int. Conf. on Computer, Communication and Control Technologies: CCCT'03, Orlando, July, August, 2003.
4. Stammermann, A., Kruse, L., Nebel, W., Pratsch, A., Schmidt, E., Schulte, M., and Schulz, A., System Level Optimization and Design Space Exploration for Low Power, in Proc. Int. Symposium on System Synthesis, Montreal, September, 2001.
5. Mehra, R., and Rabaey, J., Behavioral Level Power Estimation and Exploration, in Proc. First Int. Workshop on Low Power Design, Napa Valley, April, 1994.
6. http://www.bulldast.com/powerchecker.html.
7. Von Cölin, G., Kruse, L., Schmidt, E., Stammermann, A., and Nebel, W., Power Macro-Modelling for Firm-Macros, in Proc. PATMOS, Göttingen, September, 2000.
8. Schmidt, E., von Cölln, G., Kruse, L., Theeuwen, F., and Nebel, W., Automatic Nonlinear Memory Power Modelling, in Proc. Design, Automation and Test in Europe (DATE), Munich, March, 2001.
9. Girczyc, E.F., and Knight, J.P., An ADA to Standard Cell Hardware Compiler Based on Graph Grammers and Scheduling, in Proc. IEEE Int. Conf. on Computer Design, October, 1984.
10. Raghunathan, A., and Jha, N.K., Behavioral Synthesis for Low Power, in Proc. IEEE Int. Conf. on Computer Design, October, 1994.
11. Zhong, L., and Jha, N.K., Interconnect-aware High-level Synthesis for Low Power, in Proc. Conference on Computer Aided Design, San Jose, November, 2002.
12. Stammermann, A., Helms, D., Schulte, M., Schulz, A., and Nebel, W., Binding, Allocation and Floorplanning in Low Power High-Level Synthesis, in Proc. ACM/IEEE Int. Conference on Computer Aided Design, San Jose, November 2003.
13. Prabhakaran, P, Banerjee, P., Crenshaw, J., and Sarrafzadeh, M., Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization, in Proc. VLSI Design, Goa, January, 1999.
14. Musoll, E. and Cortadella, J., Scheduling and Resource Binding for Low Power, in Proc. Int. Symposium on System Synthesis, Cannes, September, 1995.
15. Khouri, K.S., Lakshminarayana, G., and Jha, N.K., Fast High-level Power Estimation for Control-flow Intensive Designs, in Proc. International Symposium on Low Power Electronics and Design, Monterey, August, 1998.
16. Kruse, L., Schmidt, E., Jochens, G., Stammermann, A., Schulz, A., Macii, E., and Nebel, W., Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow Graphs, IEEE Trans. On Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1, February, 2001.
17. GarciaOrtiz, A., Kabulepa, L., Murgan, T., Glesner, M., Moment Based Power Estimation in Very Deep Submicron Technologies, in Proc. ACM/IEEE Int. Conf Conference on Computer Aided Design, San Jose, November 2003.
18. Stammermann, A., Helms, D., Schulte, M., and Nebel, W., Interconnect Driven Low Power High-Level Synthesis, in Proc. PATMOS, Torino, September, 2003.
19. www.chipvision.com
20. Nebel, W., Helms, D., High-Level Power Estimation and Analysis, to appear in Christian Piguet (ed.), Low Power Electronics Design, CRC-Press, 2004