Design, modeling, and hardware correlation of a 3.2 Gb/s/pair memory channel

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 1, 2004, Pages 34-44

  Beyene, Wendemagegnehu Wendem T ^a   Yuan, Xingchao Chuck ^a   Cheng, Newton ^a   Shi, Hao ^a  

^a RAMBUS INC   (United States)

Author keywords

Bandlimiting; Fast Fourier transform; Printed circuit board

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC LOSSES; FAST FOURIER TRANSFORMS; FREQUENCY DOMAIN ANALYSIS; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT DESIGN; SEMICONDUCTING SILICON; THREE DIMENSIONAL; TIME DOMAIN ANALYSIS; WAVEFORM ANALYSIS;

BANDLIMITING; HIGH FREQUENCY EFFECT; INPUT-OUTPUT CIRCUIT;

ELECTRONICS PACKAGING;

EID: 2442486758     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.825463     Document Type: Article

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