-
2
-
-
2442440116
-
Utilization bounds for the fixed-priority scheduling of periodic task systems on identical multiprocessors
-
Department of Computer Science, The University of North Carolina, June
-
S. Baruah. Utilization bounds for the fixed-priority scheduling of periodic task systems on identical multiprocessors. Technical Report TR03-022, Department of Computer Science, The University of North Carolina, June 2003.
-
(2003)
Technical Report
, vol.TR03-022
-
-
Baruah, S.1
-
3
-
-
0001326859
-
Proportionate progress: A notion of fairness in resource allocation
-
June
-
S. Baruah, N. Cohen, G. Plaxton, and D. Varvel. Proportionate progress: A notion of fairness in resource allocation. Algorithmica, 15(6):600-625, June 1996.
-
(1996)
Algorithmica
, vol.15
, Issue.6
, pp. 600-625
-
-
Baruah, S.1
Cohen, N.2
Plaxton, G.3
Varvel, D.4
-
4
-
-
0034441433
-
Power-aware systems
-
Nov.
-
M. Bhardwaj, R. Min, and A. Chandrakasan. Power-aware systems. In Proceedings of the 34th Asilomar Conference on Signals, Systems, and Computers, volume 2, pages 1695-1701, Nov. 2000.
-
(2000)
Proceedings of the 34th Asilomar Conference on Signals, Systems, and Computers
, vol.2
, pp. 1695-1701
-
-
Bhardwaj, M.1
Min, R.2
Chandrakasan, A.3
-
5
-
-
0026853681
-
Low-power CMOS digital design
-
A. P. Chandrakasan, S. Sheng, and R. W. Brodersen. Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, 27(4):119-123, 1992.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, Issue.4
, pp. 119-123
-
-
Chandrakasan, A.P.1
Sheng, S.2
Brodersen, R.W.3
-
6
-
-
0003197503
-
The design and implementation of a dual-core platform for power-train systems
-
Detriot (MI), USA, October
-
A. Ferrari, S. Garue, M. Peri, S. Pezzini, L. Valsecchi, F. Andretta, and W. Nesci. The design and implementation of a dual-core platform for power-train systems. In Convergence 2000, Detriot (MI), USA, October 2000.
-
(2000)
Convergence 2000
-
-
Ferrari, A.1
Garue, S.2
Peri, M.3
Pezzini, S.4
Valsecchi, L.5
Andretta, F.6
Nesci, W.7
-
7
-
-
0035680674
-
Minimizing memory utilization of real-time task sets in single and multiprocessor systems-on-a-chip
-
IEEE Computer Society Press, December
-
P. Gai, G. Lipari, and M. di Natale. Minimizing memory utilization of real-time task sets in single and multiprocessor systems-on-a-chip. In Proceedings of the IEEE Real-Time Systems Symposium. IEEE Computer Society Press, December 2001.
-
(2001)
Proceedings of the IEEE Real-Time Systems Symposium
-
-
Gai, P.1
Lipari, G.2
Di Natale, M.3
-
9
-
-
0033319645
-
Power optimization of variable voltage core-based systems
-
I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava. Power optimization of variable voltage core-based systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1702-14, 1999.
-
(1999)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.18
, Issue.12
, pp. 1702-1714
-
-
Hong, I.1
Kirovski, D.2
Qu, G.3
Potkonjak, M.4
Srivastava, M.B.5
-
10
-
-
0032311886
-
On-line scheduling of hard real-time tasks on a variable voltage processor
-
N. Y., Nov. 8-12 . ACM Press
-
I. Hong, M. Potkonjak, and M. B. Srivastava. On-line scheduling of hard real-time tasks on a variable voltage processor. In International Conference on Computer Aided Design (ICCAD-98), pages 653-656, N. Y., Nov. 8-12 1998. ACM Press.
-
(1998)
International Conference on Computer Aided Design (ICCAD-98)
, pp. 653-656
-
-
Hong, I.1
Potkonjak, M.2
Srivastava, M.B.3
-
11
-
-
2442450653
-
Power-aware design synthesis techniques for distributed real-time systems
-
C. Norris and J. B. F. Jr., editors, New York, June 22-23 . ACM Press
-
D. Kang, S. Crago, and J. Suh. Power-Aware design synthesis techniques for distributed Real-Time systems. In C. Norris and J. B. F. Jr., editors, Proceedings of the Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES-01), volume 36, 8 of ACM SIGPLAN Notices, pages 20-28, New York, June 22-23 2001. ACM Press.
-
(2001)
Proceedings of the Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES-01), Volume 36, 8 of ACM SIGPLAN Notices
, vol.36
, pp. 20-28
-
-
Kang, D.1
Crago, S.2
Suh, J.3
-
12
-
-
0027799466
-
TTP - A time-triggered protocol for fault-tolerant real-time systems
-
J.-C. Laprie, editor, Toulouse, France, June . IEEE Computer Society Press
-
H. Kopetz and G. Grünsteidl. TTP - A time-triggered protocol for fault-tolerant real-time systems. In J.-C. Laprie, editor, Proceedings of the 23rd Annual International Symposium on Fault-Tolerant Computing (FTCS '93), pages 524-533, Toulouse, France, June 1993. IEEE Computer Society Press.
-
(1993)
Proceedings of the 23rd Annual International Symposium on Fault-Tolerant Computing (FTCS '93)
, pp. 524-533
-
-
Kopetz, H.1
Grünsteidl, G.2
-
13
-
-
84884679161
-
Worstcase utilization bound for EDF scheduling in real-time multiprocessor systems
-
Stockholm, Sweden, June . IEEE Computer Society Press
-
J. M. Lopez, M. Garcia, J. L. Diaz, and D. F. Garcia. Worstcase utilization bound for EDF scheduling in real-time multiprocessor systems. In Proceedings of the EuroMicro Conference on Real-Time Systems, pages 25-34, Stockholm, Sweden, June 2000. IEEE Computer Society Press.
-
(2000)
Proceedings of the EuroMicro Conference on Real-Time Systems
, pp. 25-34
-
-
Lopez, J.M.1
Garcia, M.2
Diaz, J.L.3
Garcia, D.F.4
-
14
-
-
0035311079
-
Power: A first class design constraint for future architectures
-
April
-
T. Mudge. Power: A first class design constraint for future architectures. IEEE Computer, 34(4):52-58, April 2001.
-
(2001)
IEEE Computer
, vol.34
, Issue.4
, pp. 52-58
-
-
Mudge, T.1
-
15
-
-
2442520452
-
Dynamic power management of multiprocessor systems
-
Washington - Brussels - Tokyo, Apr. IEEE
-
J. Suh, D.-I. Kang, and S. Crago. Dynamic power management of multiprocessor systems. In 16th International Parallel and Distributed Processing Symposium, page 97, Washington - Brussels - Tokyo, Apr. 2002. IEEE.
-
(2002)
16th International Parallel and Distributed Processing Symposium
, pp. 97
-
-
Suh, J.1
Kang, D.-I.2
Crago, S.3
-
17
-
-
0029488569
-
A scheduling model for reduced CPU energy
-
IEEE, editor, 1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA . IEEE Computer Society Press
-
F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced CPU energy. In IEEE, editor, 36th Annual Symposium on Foundations of Computer Science: October 23-25, 1995, Milwaukee, Wisconsin, pages 374-382, 1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA, 1995. IEEE Computer Society Press.
-
(1995)
36th Annual Symposium on Foundations of Computer Science: October 23-25, 1995, Milwaukee, Wisconsin
, pp. 374-382
-
-
Yao, F.1
Demers, A.2
Shenker, S.3
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