Fully pipelined programmable real-time (3×3) image filter based on capacitive threshold-logic gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 2072-2075

  Leblebici, Y ^a   Kepkep, A ^a   Gurkaynak, F K ^a   Ozdemir, H ^a   Cilingiroglu, U ^a  

^a ISTANBUL TECHNICAL UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; IMAGE PROCESSING; LOGIC GATES; MULTICHIP MODULES; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; THRESHOLD LOGIC;

CAPACITIVE THRESHOLD LOGIC (CTL) GATES; PROGRAMMABLE TWO DIMENSIONAL IMAGE FILTERS;

DIGITAL FILTERS;

EID: 0030700165     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)