A novel technique for steady state analysis for VLSI circuits in partially depleted SOI

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 832-836

  Joshi, R V ^a   Kroell, K ^b   Chuang, C T ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; PHASE LOCKED LOOPS; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE; SWITCHES; THRESHOLD VOLTAGE;

CIRCUIT SIMULATIONS; IONIZATION CURRENTS; SWITCHING CYCLES; VOLTAGE INITIALIZATION;

VLSI CIRCUITS;

EID: 2342636340     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. R. V. Joshi and K. Kroell,"SOI design technique", US Patent 6442735, Aug 27, 2002.
2. D. J. Schepis et al., "A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM," Tech. Digest, IEDM, 1997, pp.587-590.
3. R. V. Joshi et al., "A 666 MHz self-resetting 8 Port, 32×64 bits register file and latch in .25 μm SOI technology," Proc. IEEE Int'l SOI Conf., 1998, pp. 131-132.
4. D. Allen et al., "A 0.2 μm 1.8 V SOI 550 MHz 64b PowerPC microprocessor with Cu interconnects", Dig. Tech. Papers, ISSCC, 1999, pp. 438-439.
5. C. T. Chuang, "Design considerations of SOI digital CMOS VLSI, Proc. IEEE Int'l SOI Conf., 1998, pp. 5-8.
6. R. V. Joshi et al., "A high performance SRAMs in 1.5 V. 0.18 μm partially depleted SOI technology", Dig. of Tech. Papers, Symp. VLSI Circuits, 2002, pp. 74-77.
7. th Design Automation Conf., 1999, pp. 709-714.
8. S. K. H. Fung et al., "Controlling floating body effects for 0.13 μm and 0.10 μm SOI CMOS," Tech. Digest, IEDM, 2000, pp. 231-234.