660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology

IEEE International SOI Conference

Volumn , Issue , 1998, Pages 131-132

  Joshi, R V ^a   Hwang, W ^a   Henkels, W H ^a   Wilson, S ^a   Rausch, W ^a   Shahidi, G ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

REGISTER FILES;

FLIP FLOP CIRCUITS;

EID: 0032306395     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)