An efficient algorithm to construct reduced visibility graph and its FPGA implementation

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 1057-1062

  Priya, T K ^a   Sridharan, K ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

Binary Search; FPGA Implementation; Parallel Algorithm and Architecture; Reduced Visibility Graph

Indexed keywords

BINARY SEARCH; FPGA IMPLEMENTATION; PARALLEL ALGORITHM AND ARCHITECTURE; REDUCED VISIBILITY GRAPH;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER GRAPHICS; COMPUTER SIMULATION; DEGREES OF FREEDOM (MECHANICS); GRAPH THEORY; MOTION PLANNING; VLSI CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2342564948     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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