Low resistivity p+ polycrystalline silicon deposition at low temperatures with SiH4/BCl3

Electrochemical and Solid-State Letters

Volumn 7, Issue 5, 2004, Pages

  Herner, S B ^a   Konevecki, M ^a   Raghuram, U ^a   Sivaram, S ^a   Clark, M H ^b  

^a Matrix Semiconductor   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; CMOS INTEGRATED CIRCUITS; DEPOSITION; ELECTRIC CONDUCTIVITY; INTEGRATED CIRCUITS; LOW TEMPERATURE EFFECTS; RESISTORS; SECONDARY ION MASS SPECTROMETRY; THERMAL EFFECTS; THIN FILMS; TRENCHING;

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS); DEPOSITION RATE; LINE RESISTORS; SECONDARY ION MASS SPECTROMETRY (SIMS);

POLYSILICON;

EID: 2342501808     PISSN: 10990062     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1691531     Document Type: Article

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