A single-chip JPEG2000 encode processor capable of compressing D1-images at 30 frames/s without tile division

IEICE Transactions on Electronics

Volumn E87-C, Issue 4, 2004, Pages 448-456

  Yamauchi, Hideki ^a   Okada, Shigeyuki ^a   Taketa, Kazuhiko ^a   Ohyama, Tatsushi ^a  

^a SANYO ELECTRIC CO LTD   (Japan)

Author keywords

Image compression; JPEG2000; Multimedia; System LSI; Wavelet

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETERIORATION; IMAGE CODING; IMAGE COMPRESSION; IMAGE QUALITY; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; REAL TIME SYSTEMS; WAVELET TRANSFORMS;

BOUNDARY NOISE; DISCRETE WAVELET TRANSFORMS (DWT); HIERARCHICAL ENCODING;

VLSI CIRCUITS;

EID: 2342468830     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. ISO/me IS 15444-1, "Information technology - JPEG2000 image coding system - Part 1: Core coding system," ISO/IECJTC1/SC29/WG1, Dec. 2000.
2. ISO/IEC IS 15444-1, "Information technology - JPEG2000 image coding system - Part 1: Core coding system," AMENDMENT 1: Code stream restrictions, March 2002.
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9. H. Yamauchi, S. Okada, K. Taketa, T. Ohyama, Y. Matsuda, T. Mori, S. Okada, T. Watanabe, Y. Matsuo, Y. Yamada, T. Ichikawa, and Y. Matsushita, "Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications," ISSCC Digest of Technical Papers, pp.46-47, 2003.