One-chip 15 frame/s mega-pixel real-time image processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 144-145

  Yamauchi, H ^a   Okada, S ^a,a   Matsuda, Y ^a   Mori, T ^a   Watanabe, T ^a   Kobayashi, A ^a   Ogura, I ^a   Harada, Y ^a  

^a SANYO ELECTRIC CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CHARGE COUPLED DEVICES; COMPUTER ARCHITECTURE; DECODING; DYNAMIC RANDOM ACCESS STORAGE; HIGH DEFINITION TELEVISION; IMAGE CODING; IMAGE COMPRESSION; IMAGE QUALITY; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING; STANDARDS; TRANSISTORS;

CLOCK GEAR TECHNIQUE; JOINT PICTURE EXPERTS GROUP (JPEG) STANDARDS; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS; POWER CONSUMPTION;

LSI CIRCUITS;

EID: 0035062666     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isscc.2001.912579     Document Type: Conference Paper

References (1)

1. System on a chip for digital still camera with VGA-Size video clip shooting