Fast, layout-aware validation of test-vectors for nanometer-related timing failures

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 597-602

  Kokrady, Aman ^a   Ravikumar, C P ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

At Speed Testing; Crosstalk; IR Drop; Test Validation; Timing Failure

Indexed keywords

AT SPEED TESTING; IR DROP; PROCESS-VOLTAGE-TEMPERATURE (PVT); TEST VALIDATION; TIMING FAILURE;

ALGORITHMS; COMPUTER SIMULATION; CROSSTALK; LOGIC GATES; MATHEMATICAL MODELS; NANOTECHNOLOGY; PROBLEM SOLVING; VECTORS; VOLTAGE MEASUREMENT;

COMBINATORIAL CIRCUITS;

EID: 2342466046     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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