Perceptron-based branch confidence estimation

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn 10, Issue , 2004, Pages 265-274

  Akkary, Haitham ^a,b   Srinivasan, Srikanth T ^b   Koltur, Rajendar ^a   Patil, Yogesh ^a   Refaai, Wael ^a  

^a PORTLAND STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP PIPELINE PROCESSORS; MULTITHREADING; PIPELINE GATING; PROGRAM EXECUTION;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; LOGIC DESIGN; NEURAL NETWORKS; PARAMETER ESTIMATION;

PROGRAM PROCESSORS;

EID: 2342460917     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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