Instruction-level microprocessor modeling of scientific applications

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1615, Issue , 1999, Pages 29-40

  Cameron, Kirk W ^a,b   Luo, Yong ^b   Scharzmeier, James ^c  

^a Louisiana State University   (United States)

^b LOS ALAMOS NATIONAL LABORATORY   (United States)

^c HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SCIENCE; COMPUTERS;

ACCELERATED STRATEGIC COMPUTING INITIATIVES; ANALYTICAL FORMULAS; ARCHITECTURAL PARAMETERS; PERFORMANCE COUNTERS; PROCESSOR UTILIZATION; SCIENTIFIC APPLICATIONS; SUPERSCALAR MICRO-PROCESSORS; US DEPARTMENT OF ENERGY;

ARTIFICIAL INTELLIGENCE;

EID: 22644451909     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0094909     Document Type: Conference Paper

References (12)

1. Albonesi, D. H., and Koren, I., A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques, International Journal of Parallel Programming, Vol. 24, No. 3, 1996.
2. Emma, P. G., and Davidson, E. S., Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance, IEEE Transactions on Computers, Vol. C-36, No. 7, July 1987.
3. De Gloria, A., Ancarani, F., Bellotti, F., and Olivieri, M., Instruction level analytic prediction of parallel CPU architecture performance, IIS 97, Dec. 1997.
4. Migliardi, M., and Maresca, M., Modelling Instruction Level Parallel Architectures Efficiency in Image Processing Applications, International Conference on High Performance Computing and Networking, Vienna, Austria, April 1997.
5. MacDougall, M. H., Instruction-Level Program and Processor Modeling, IEEE Computer, July 1984
6. Lübeck, O. M, Luo, Y., and Wasserman, H. J. et al, An Empirical Hierarchical Memory Model Based on Hardware Performance Counters, PDPTA'98, Las Vegas, July 13-16, 1998.
7. Sun, X. H., Cameron, K. W., et al., A Hierarchical Statistic Methodology for Advanced Memory System Evaluation, accepted by IPPS99, Sept. 1998.
8. Luo, Y. and Cameron, K. W., Instruction-level Characterization of Scientific Computing Application using Hardware Performance Counters, Workshop on Workload Characterization at Micro-31, Nov. 1998.
9. Bianchini, R., Lim, B., Evaluating the Performance of Multithreading and Prefetching in Multiprocessors, Journal of Parallel and Distributed Computing, N. 37, p83-97, 1996.
10. Luo, Y., and Cameron, K. Instruction-level Performance Modeling and Characterization of Multimedia Applications, Los Alamos Unclassified Technical Report #99-303, Jan. 1999.
11. Hennessy, J. L., and Patterson, D. A., Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., p35-37, 1996.
12. Turner, S. (SGI/Cray), Private Communications, Mar. 1998.