A Mean Value Analysis multiprocessor model incorporating superscalar processors and latency tolerating techniques

International Journal of Parallel Programming

Volumn 24, Issue 3, 1996, Pages 235-263

  Albonesi, David H ^a   Koren, Israel ^b  

^a University of Massachusetts   (United States)

^b NONE

Author keywords

Latency tolerating techniques; Mean value analysis; Performance evaluation; Shared memory multiprocessors; Superscalar processors

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; LOGIC DESIGN; PERFORMANCE;

LATENCY TOLERANCING TECHNIQUES; MEAN VALUE ANALYSIS; SHARED MEMORY MULTIPROCESSORS; SUPERSCALAR PROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 0030164201     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF03356750     Document Type: Article

References (23)

1. D. H. Albonesi and I. Koren, An analytical model of high performance superscalar-based multiprocessors, Intl. Conf. on Parallel Architectures and Compilation Techniques, pp. 194-203(1995).
2. E. D. Lazowska, J. Zahorjan, G. S. Graham, and K. C. Sevcik, Qualitative System Performance, Computer Analysis Using Queuing Network Models, Prentice Hall, Englewood Cliffs, New Jersey (1991).
3. D. Lenoski, J. Laudon, T. Joe, D. Nakahira, L. Stevens, A. Gupta, and J. Hennessy, The DASH prototype: implementation and performance, Intl J. Symp. on Computer Architecture, pp. 92-103 (1992).
4. J. R. Goodman and P. J. Woest, The Wisconsin multicube: a new large-scale cachecoherent multiprocessor, /;;/J. Symp. on Computer Architecture, pp. 422-431 (1988).
5. R. Jog, P. L. Vitale, and J. R. Callister, Performance evaluation of a commercial cachecoherent shared memory multiprocessor, Intl. Conf. on Measurement and Modeling of Computer Systems, pp. 173-182 (1990).
6. M. Chiang and G. S. Sohi, Experience with Mean Value Analysis models for evaluating shared bus, throughput-oriented multiprocessors, Intl. Conf. on Measurement and Modeling of Computer Systems, pp. 90-100 (1991).
7. M. K. Vernon, E. D. Lazowska, and J. Zahorjan, An accurate and efficient performance analysis technique for multiprocessor snooping cache consistency protocols, Infl. Symp. on Computer Architecture, pp. 308-315 (1988).
8. M. Chiang and G. S. Sohi, Evaluating design choices for shared bus multiprocessors in a throughput-oriented environment, IEEE Trans, on Computers, -41(3):297-317 (1992).
9. D. H. Albonesi and I. Koren, Tradeoffs in the design of single chip multiprocessors, Intl. Conf, on Parallel Architectures and Compilation Techniques (PACT'94), pp. 25-34 (1994).
10. S. T. Leutenegger and M. K. Vernon, A mean-value performance analysis of a new multiprocessor architecture, Infl. Conf. on Measurement and Modeling of Computer Systems, pp. 167-176(1988).
11. M. K. Vernon, R. Jog, and G. S. Sohi, Performance analysis of hierarchical cache-consistent multiprocessors, Performance Evaluation, 9(4):287-302 (1989).
12. J. Torrellas, J. Hennessy, and T. Weil, Analysis of critical architectural and program parameters in a hierarchical shared-memory multiprocessor, Infl. Conf. on Measurement and Modeling of Computer Systems, pp. 163-172 (1990).
13. P. K. Dubey, G. B. Adams III, and M. J. Flynn, Instruction window size trade-offs and characterization of program parallelism, IEEE Trans, on Computers, 43(4):431-442 (1994).
14. T. Asprey, G. S. Averill, E. DeLano, R. Mason, B. Weiner, and J. Yetter, Performance features of the PA7IOO microprocessor, IEEE Micro, 13(3):22-35 (1993).
15. E. McLellan, The Alpha AXP architecture and 21064 processor, IEEE Micro, 13(3):36-47 (1993).
16. D. Alpert and D. Avnon, Architecture of the Pentium microprocessor, IEEE Micro, 13(3):11-21 (1993).
17. C. P. Thacker, D. G. Conroy, and L. C. Stewart, The Alpha demonstration unit: a highperformance multiprocessor for software and chip development, Digital Technical Journal, 4(4):51-65 (1992).
18. G. Sohi and M. Franklin, High-bandwidth data memory systems for superscalar processors, Int'l. Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 53-61 (1991).
19. K. I. Farkas and N. P. Jouppi, Complexity/performance tradeoffs with non-blocking loads, Intl. Symp. on Computer Architecture, pp. 211-222 (1994).
20. R. L. Sites, Alpha AXP architecture, Digital Technical journal, 4(4):19-34 (1992).
21. B. R. Allison and C. van Ingen, Technical description of the DEC 7000 and DEC 10000 AXP family, Digital Technical Journal, 4(4): 100-110 (1992).
22. J. H . Edmondson, et al., Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor, Digital Technical Journal, 7(1):119-135 (1994).
23. D. H. Albonesi and I. Koren, Architecture and technology tradeoffs in the design of nextgeneration multiprocessor servers, IEEE Symp. on Parallel and Distributed Processing, pp. 174-181 (1995).