An FPGA implementation of the GPRS encryption algorithm 3 (GEA3)

Journal of Circuits, Systems and Computers

Volumn 14, Issue 2, 2005, Pages 217-231

  Kitsos, P ^a   Galanis, M D ^a   Koufopavlou, O ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

Block cipher; Double edge triggered (DET) pipeline; GEA3; GPRS security; KASUMI; S BOX; Stream cipher

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; CRYPTOGRAPHY; DATA ACQUISITION; ROM; SILICON;

BLOCK CIPHER; DOUBLE EDGE TRIGGERED (DET) PIPELINE; GEA3; GENERAL PACKET RADIO SERVICE (GPRS) SECURITY; KASUMI; S-BOX; STREAM CIPHER;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 22344432881     PISSN: 02181266     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0218126605002337     Document Type: Article

References (22)

1. ETSI TS 148 018. Digital cellular telecommunications system (Phase 2+), General Packet Radio Service (GPRS); Base Station System (BSS) - Serving GPRS Support Node (SGSN), BSS GPRS Protocol, May 2002, http://webapp.etsi.org/action/ PU/20020611/ts_148018v050300p.pdf.
2. ETSI/SAGE, Specification of the A5/3 Encryption Algorithms for GSM and EDGE, and GEA3 Encryption Algorithm for GPRS, Document 1: A5/3 and GEA3 Specifications, ETSI/SAGE, May 2002, http://www.3gpp.org/ftp/Specs/archive/ 55_series/55.216/.
3. ETSI/SAGE, Specification of the 3GPP Confidentiality and Integrity Algorithms, Document 2: KASUMI Specification, ETSI/SAGE, December 1999, http://www.3gpp.org/ftp/Specs/archive/35_series/35.202/.
4. K. Marinis, N. K. Moshopoulos, F. Karoubalis and K. Z. Pekmestzi, On the hardware implementation of the 3GPP confidentiality and integrity algorithms, Proc. 4th Int. Conf. Information Security, ISC 2001, Malaga, Spain, 1-3 October 2001, pp. 248-265.
5. K. Marinas, N. K. Moshopoulos, F. Karoubalis and K. Z. Pekmestzi, An area optimized hardware implementation of the 3GPP confidentiality and integrity algorithms, Proc. 8th Conf. Optimization of Electrical and Electronic Equipment, OPTIM 2002, Brasov, Romania, 16-17 May 2002.
6. H. Kim, Y. Choi, M. Kim and H. Ryu, Hardware implementation of 3GPP KASUMI crypto algorithm, 2002 Int. Technical Conf. Circuits/Systems, Computers and Communications (ITC-CSCC), Vol. 1, 16-19 July 2002, Phuket, Thailand, pp. 317-320.
7. A. Satoh and S. Morioka, Small and high-speed hardware architectures for the 3GPP standard cipher KASUM, Proc. 5th Int. Conf. Information Security, ISC 2002, Sao Paulo, Brazil, 30 September-2 October 2002, Lecture Notes in Computer Science, Vol. 2433 (2002).
8. Recommendation for block cipher modes of operation, methods and techniques, National Institute of Standards and Technology (NIST), Technology Administration, U.S. Department of Commerce, Special Publication, http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf.
9. ETSI/SAGE, Specification of the 3GPP Confidentiality and Integrity Algorithms Document 1: f8 and f9 specification, ETSI/SAGE, September 2000, http://www.3gpp.org/ftp/Specs/archive/35.series/35.201/.
10. M. Matsui, New block encryption algorithm MISTY, Fast Software Encryption '97, Vol. 1267 of LNCS (Springer-Verlag, 1997), pp. 54-68.
11. J. Wallén, Design principles of the KASUMI block cipher, HUT TML 2000, Tik-110.501 Seminar on Network Security, http://www.niksula.cs.hut.fi/ ~jwallen/kasumi/kasumi.html.
12. 3rd Generation Partnership Project; Security Algorithms Group of Experts (SAGE); Report on the Evaluation of 3GPP Standard Confidentiality and Integrity Algorithms, 3GPP KASUMI Evaluation Report, http://www.3gpp.org/tb/other/ algorithms/KASUMI_Eval_rep_v20.pdf.
13. B. Schneier, Applied Cryptography-Protocols and Source Code in C, 2nd edn. (John Wiley and Sons, New York, 1996).
14. Mitsubishi Electric Corporation's, Information Security Technology, MISTY, KASUMI, Camellia & Security Solutions, http://www.security.melco.co. jp/SecWWW/index/02e/melsecE.htm.
15. M. Afghahi and J. Yuan, Double edge-triggered D flip-flops for high speed CMOS circuits, IEEE J. Solid-State Circuits 26 (1991) 1168-1170.
16. W. Chung, T. Lo and M. Sachdev, A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops, IEEE Trans. Very Large Scale Integration (VLSI) 10 (2002) 913-918.
17. ETSI/SAGE, Specification of the A5/3 Encryption Algorithms for GSM and EDGE, and the GEA3 Encryption Algorithm for GPRS Document 2: implementors' Test Data, ETSI/SAGE, May 2002.
18. ETSI/SAGE, Specification of the A5/3 Encryption Algorithms for GSM and EDGE, and the GEA3 Encryption Algorithm for GPRS Document 3: Design Conformance Test Data, ETSI/SAGE, May 2002.
19. Xilinx Inc., San Jose, California, Virtex, 2.5 V Field Programmable Gate Arrays, 2003, www.xilinx.com.
20. J. Cong and Y.-Y. Hwang, Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 20 (2001) 1077-1090.
21. M. Rawski, L. Jozwiak and T. Luba, Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures, Elsevier J. Syst. Architectures 47 (2001) 137-155.
22. ETSI/SAGE, Specification of the A5/3 Encryption Algorithms for GSM and EDGE, and GEA3 Encryption Algorithm for GPRS, Document 4: Design and Evaluation Report, ETSI/SAGE, May 2002, http://www.3gpp.org/ftp/Specs/archive/55_series/55. 919/.