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Volumn 15, Issue 2 PART I, 2005, Pages 445-448

A study for an improved design of front-end circuit of superconducting analog-to-digital converter

Author keywords

Analog to digital converter; Demultiplexer; Front end circuit; Single flux quantum

Indexed keywords

DATA COMMUNICATION SYSTEMS; DATA TRANSFER; DEMULTIPLEXING; JOSEPHSON JUNCTION DEVICES; MODULATORS; SHIFT REGISTERS; SIGNAL PROCESSING; SQUIDS; SUPERCONDUCTING DEVICES; SYNCHRONIZATION; TREES (MATHEMATICS);

EID: 22044434992     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2005.849870     Document Type: Conference Paper
Times cited : (8)

References (14)
  • 1
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  • 2
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    • J. X. Przybysz, D. L. Miller, E. H. Naviasky, and J. H. Kang, "Josephson sigma-delta modulator for high dynamic range A/D conversion," IEEE Trans. Appl. Supercond., vol. 3, pp. 2732-2735, Mar. 1993.
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  • 3
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    • Superconducting high-resolution A/D converter based on phase modulation and multichannel timing arbitration
    • Mar.
    • S. V. Rylov and R. P. Robertazzi, "Superconducting high-resolution A/D converter based on phase modulation and multichannel timing arbitration," IEEE Trans. Appl. Supercond., vol. 5, pp. 2260-2263, Mar. 1995.
    • (1995) IEEE Trans. Appl. Supercond. , vol.5 , pp. 2260-2263
    • Rylov, S.V.1    Robertazzi, R.P.2
  • 5
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    • Superconducting bandpass ΣΔ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate
    • Dec.
    • J. F. Bulzacchelli, H. S. Lee, J. A. Misewich, and M. B. Kelchen, "Superconducting bandpass ΣΔ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate," IEEE J. Solid-State Circuits, vol. 37, pp. 1695-1702, Dec. 2002.
    • (2002) IEEE J. Solid-state Circuits , vol.37 , pp. 1695-1702
    • Bulzacchelli, J.F.1    Lee, H.S.2    Misewich, J.A.3    Kelchen, M.B.4
  • 7
    • 0041439949 scopus 로고    scopus 로고
    • High-speed operation of demultiplexer up to 56 GHz
    • Jun.
    • F. Furuta, K. Saitoh, and K. Takagi, "High-speed operation of demultiplexer up to 56 GHz," IEEE Trans. Appl. Supercond., vol. 13, pp. 567-570, Jun. 2003.
    • (2003) IEEE Trans. Appl. Supercond. , vol.13 , pp. 567-570
    • Furuta, F.1    Saitoh, K.2    Takagi, K.3
  • 8
    • 0035268583 scopus 로고    scopus 로고
    • Interface circuit using JTL's as control lines of SQUID array
    • Mar.
    • Y. Tarutani, K. Saitoh, and K. Takagi, "Interface circuit using JTL's as control lines of SQUID array," IEEE Trans. Appl. Superconduct., vol. 11, pp. 341-344, Mar. 2001.
    • (2001) IEEE Trans. Appl. Superconduct. , vol.11 , pp. 341-344
    • Tarutani, Y.1    Saitoh, K.2    Takagi, K.3
  • 9
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    • Design of front-end circuit for superconductive a/d converter and demonstration of operation up to 43 GHz
    • Mar.
    • F. Furuta, K. Saitoh, and K. Takagi, "Design of front-end circuit for superconductive a/d converter and demonstration of operation up to 43 GHz," IEEE Trans. Appl. Supercond., vol. 14, pp. 40-45, Mar. 2004.
    • (2004) IEEE Trans. Appl. Supercond. , vol.14 , pp. 40-45
    • Furuta, F.1    Saitoh, K.2    Takagi, K.3
  • 10
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    • H. Suzuki, A. Inoue, T. Imanura, and S. Hasuo, "A Josephson driver to interface Josephson junctions to semiconductor transistors," in IEDM Tech. Dig., Dec. 1988, pp. 290-293.
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    • Suzuki, H.1    Inoue, A.2    Imanura, T.3    Hasuo, S.4
  • 11
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    • A new type of demultiplexer for gaining timing margin
    • to be published
    • F. Furuta and K. Saitoh, "A new type of demultiplexer for gaining timing margin," Physica C, 2004, to be published.
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    • Furuta, F.1    Saitoh, K.2
  • 12
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  • 14
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    • S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380 ps, 9.5 mW Josephson 4-kbit RAM operated at a high bit yield," IEEE Trans. Appl. Supercond., vol. 5, pp. 2447-2452, Jun. 1995.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.