CMOS transistor mismatch model with temperature effect for HSPICE and SPECTRE

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn 2, Issue , 2004, Pages 1139-1142

  Tan, Philip Beow Yew ^a,b   Kordesch, Albert Victor ^a   Sidek, Othman ^b  

^a SILTERRA MALAYSIA SDN BHD   (Malaysia)

^b SCHOOL OF CHEMICAL ENGINEERING   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; LINEAR EQUATIONS; MATHEMATICAL MODELS; SIGNAL PROCESSING; THERMAL EFFECTS; THRESHOLD VOLTAGE;

CIRCUIT SIMULATION; HSPICE; SPECTRE; TRANSISTOR DESIGN;

TRANSISTORS;

EID: 21644485738     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. B. Y. Tan and A. V. Kordesch, "Thermal Effect on Matching of MOS Transistor Threshold Voltage and Drain Current," IEEE National Symposium on Microelectronics, pp. 35-38 (2003).
2. A. Maxim and M. Gheorghe "A Novel Physical Based Model of Deep-Submicron CMOS Transistors Mismatch for Monte Carlo SPICE Simulation, " IEEE International Symposium on Circuit and Systems, vol. 5 (2001).
3. M. Pelgrom, A. Duinmaijer and A. Welbers, "Matching Properties of MOS Transistors," IEEE Journal of Solid State Circuits, vol. 24, pp. 1433-1439 (1989).
4. T. S. Gotarredona and B. L. Barranco, "A New Five-Parameter MOS Transistor Mismatch Model," IEEE Electron Device Letters, vol. 21, no. 1 (2000).
5. S. Wong, K. Pan and D. Ma, "A CMOS Mismatch Model and Scaling Effects," IEEE Electron Device Letter, vol. 18, no. 6, pp. 261-263 (1997).