Technologies for Scaling Vertical Transistor DRAM Cells to 70nm

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 59-60

  Divakaruni, R ^a   Redens, C ^a   Belyansky, M ^a   Chudzik, M ^a   Park, D G ^a   Saroop, S ^a   Chidambarrao, D ^a   Weybright, M ^a   Akatsu, H ^a   Economikos, L ^a   Settlemyer, K ^a   Strane, J ^a   Dobuzinsky, D ^a   Edleman, N ^a   Feng, G ^a   Li, Y ^a   Jammy, R ^a   Crabbe E ^a   Bronner, G ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; ELECTRIC RESISTANCE; EMBEDDED SYSTEMS; LOGIC PROGRAMMING; MICROPROCESSOR CHIPS; TRANSISTORS; DYNAMIC RANDOM ACCESS STORAGE;

VERTICAL TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE; ASPECT RATIO;

CELL MODIFICATIONS; DEEP TRENCH; DRAM CELLS; DRAM CHIPS; ENABLING TECHNOLOGIES; FILL RESISTANCE; HIGH ASPECT RATIO; LOW RESISTANCE; SCALINGS; VERTICAL TRANSISTORS;

EID: 0141426829     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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