The influence of the stacked and double material gate structures on the short channel effects in SOI MOSFETs

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2004, Pages 68-71

  Behnam, A ^a   Fathi, E ^a   Hashemi, P ^a   Esfandiarpoor, B ^a   Fathipour, M ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOUNDARY CONDITIONS; COMPUTER SIMULATION; DATA FLOW ANALYSIS; DATA STRUCTURES; ELECTRIC FIELD EFFECTS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; PERSONAL DIGITAL ASSISTANTS;

DATA FLOW GRAPH (DFG); DUAL METAL STACK GATE (DMSG); POISON EQUATION; POST-PROCESSINGS;

MOSFET DEVICES;

EID: 21644473219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. T. Ohno, et. al., "Experimental 0.25 um gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique", IEEE Trans. Electron Devices, vol. 42, 1995, p. 1481.
2. M. Saxena et. al, "Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET", Solid-State Electronics, vol. 47, 2003, pp. 2131-2134.
3. M. J. Kumar and Anurag Chaudhry, "Two-dimensional analysis modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs", IEEE Trans. Electron Devices, vol. 51, 2004, p. 569.
4. W. Long, H. Ou, J. Kuo, and K. K. Chin, "Dual Material Gate(DMG) Field effect transistor", IEEE Trans. Electron Devices, vol.46, 1999, p.865.
5. ISE TCAD manual, ver. 7.0.
6. K. K. Young, "Short channel effect in fully depleted SOI MOSFETs", IEEE Trans. Electron Devices, vol. 36, 1989, pp. 399-402.