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Volumn , Issue , 2004, Pages 99-102

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

Author keywords

[No Author keywords available]

Indexed keywords

GATE LEAKAGE; SCANNING SPREADING RESISTANCE MEASUREMENT (SSRM); SPER TECHNOLOGY; VOLTAGE DROP; DEPLETION REGION; DESIGN SPACES; DRIVE CURRENTS; GATE ELECTRODES; GATE-LENGTH; JUNCTION FORMATION; JUNCTION LEAKAGES; OFF STATE; PMOSFET;

EID: 21644473099     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (5)
  • 1
    • 21644449027 scopus 로고    scopus 로고
    • Improvement of threshold voltage roll-off by ultra shallow junction formed by flash lamp annealing
    • T. Ito et al., "Improvement of Threshold Voltage Roll-off by Ultra shallow Junction Formed by Flash Lamp Annealing", VLSI Symp. Tech. Dig., 2003
    • (2003) VLSI Symp. Tech. Dig.
    • Ito, T.1
  • 2
    • 0842266590 scopus 로고    scopus 로고
    • Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS
    • A. Shima et al., "Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS", IEDM Tech. Dig., pp.493, 2003
    • (2003) IEDM Tech. Dig. , pp. 493
    • Shima, A.1
  • 3
    • 4544361502 scopus 로고    scopus 로고
    • High performance CMOSFET technology for the 45nm generation
    • A. Oishi et al., "High Performance CMOSFET Technology for the 45nm generation", VLSI Symp. Tech. Dig., pp.166, 2004.
    • (2004) VLSI Symp. Tech. Dig. , pp. 166
    • Oishi, A.1
  • 4
    • 21644471124 scopus 로고    scopus 로고
    • SPER junction optimization in 45nm CMOS devices
    • R. Lindsay et al., "SPER junction optimization in 45nm CMOS devices", IWJT, 2004.
    • (2004) IWJT
    • Lindsay, R.1
  • 5
    • 4544335208 scopus 로고    scopus 로고
    • 2 based high-k gate dielectrics as a candidate for low power applications
    • 2 based high-k gate dielectrics as a candidate for low power applications", VLSI Symp. Tech. Dig., pp.190, 2004.
    • (2004) VLSI Symp. Tech. Dig. , pp. 190
    • Anil, K.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.