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Volumn , Issue , 2004, Pages 99-102
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Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices
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Author keywords
[No Author keywords available]
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Indexed keywords
GATE LEAKAGE;
SCANNING SPREADING RESISTANCE MEASUREMENT (SSRM);
SPER TECHNOLOGY;
VOLTAGE DROP;
DEPLETION REGION;
DESIGN SPACES;
DRIVE CURRENTS;
GATE ELECTRODES;
GATE-LENGTH;
JUNCTION FORMATION;
JUNCTION LEAKAGES;
OFF STATE;
PMOSFET;
DIELECTRIC MATERIALS;
DIFFUSION;
ELECTRIC POTENTIAL;
ELECTRIC RESISTANCE;
ELECTRODES;
EXTRAPOLATION;
GATES (TRANSISTOR);
RAPID THERMAL ANNEALING;
SCANNING;
SEMICONDUCTOR DOPING;
THERMAL EFFECTS;
TRANSMISSION ELECTRON MICROSCOPY;
MOSFET DEVICES;
REFRACTORY METAL COMPOUNDS;
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EID: 21644473099
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (15)
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References (5)
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