Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 515-518

  Park, Seong Geon ^a   Jin, Beom Jun ^a   Lee, Hye Lan ^a   Park, Hong Bae ^a   Jeon, Taek Soo ^a   Cho, Hag Ju ^a   Kim, Sang Yong ^a   Jang, Soo Ik ^a   Kang, Sang Bom ^a   Yu Shin, Gyun ^a   Chung, U In ^a   Moon, Joo Tae ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON MOBILITY; FERMI LEVEL; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; LEAKAGE CURRENTS; MOS DEVICES; THERMODYNAMIC STABILITY; TRANSMISSION ELECTRON MICROSCOPY;

FERMI-LEVEL PINNING; GATE DIELECTRICS; GATE LEAKAGE CURRENT; RECESS CHANNEL ARRAY TRANSISTORS (RCAT);

DIELECTRIC MATERIALS;

EID: 21644448703     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Y. J. Park and K. Kim, "COB stack DRAM cell technology beyond 100nm technology node," IEDM Tech Dig. p391 (2001).
2. C. Hobbs et al., "Fermi level pinning at the Poly-Si/Metal oxide interface," Symp. VLSI Tech. p9 (2003).
3. J. Y. Kim et al., "The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88nm feature size and beyond," Symp. VLSI Tech. p11 (2003).