Device design consideration for 50 nm dynamic random access memory using bulk FinFET

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 44, Issue 4 B, 2005, Pages 2176-2179

  Han, Kyoung Rok ^a   Choi, Byung Kil ^a   Park, Tai Su ^b   Yoon, Euijoon ^b   Chung, In Young ^c   Lee, Jong Ho ^a  

^a Kyungpook National University   (South Korea)

^b Seoul National University   (South Korea)

^c Gyeongsang National University   (South Korea)

Author keywords

Body tied; Bulk; FinFET; Lightly doped drain (LDD); Non overlap

Indexed keywords

DOPING (ADDITIVES); DYNAMIC RANDOM ACCESS STORAGE; ELECTRODES; ELECTRON TUNNELING; HEAT TRANSFER; LEAKAGE CURRENTS; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

BODY-TIED; BULK; FINFET; LIGHTLY DOPED DRAIN (LDD); NON-OVERLAP;

MOSFET DEVICES;

EID: 21244454027     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.44.2176     Document Type: Conference Paper

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