Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1998, Pages 70-75

  Ibrahim Hajj, Nikolaos Bellas ^a   Polychronopoulos, Constantine ^a   Stamoulis, George ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; SIMULATION; SWITCHING;

HIGH PERFORMANCE MICROPROCESSORS; MEMORY HIERARCHY; SIGNAL SWITCHING ACTIVITY;

BUFFER STORAGE;

EID: 0031635001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)