Pipelining designs with loop-carried dependencies

Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Volumn , Issue , 2004, Pages 255-262

  Styles, Henry ^a   Thomas, David Barrie ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; CONSTRAINT THEORY; DISTRIBUTED COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; FRACTALS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; SCHEDULING;

FRACTAL SET GENERATORS; LOOP-CARRIED DEPENDENCIES; PIPELINE DESIGNS; RE-ASSEMBLING;

DATA FLOW ANALYSIS;

EID: 20844449877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Celoxica Limited. www.celoxica.com.
2. G.C. Kirkham, J.R. Gurd and I. Watson. The manchester prototype dataflow computer. Communications of the ACM, 28(1), 1985.
3. O. Mencer, H. Hubert, M. Morf and M.J. Flynn. StReAm: Object-oriented programming of stream architectures using PAM-blox. Field Programmable Logic and Applications. LNCS 1896, Springer, 2000.
4. S. Tongsima et al. Communication-sensitive loop scheduling for DSP applications. IEEE Trans. on Signal Processing, 45(5), 1997.
5. H. Styles and W. Luk. Branch optimisation techniques for hardware compilation. Field Programmable Logic and Applications. LNCS 2778, Springer, 2003.
6. A.H. Veen. Dataflow machine architecture. ACM Computing Surveys, 18(4), 1986.
7. M. Wolfe. High performance compilers for parallel computing. Addison-Wesley, Ma, 1995.
8. C. Xu and V. Chaudhary. Time-stamping algorithms for parallelization of loops at run-time. Proc. Int. Parallel Processing Symposium. IEEE Press, 1997.