Probing the issues for Cu/low-k wire bonding

Solid State Technology

Volumn 47, Issue 4, 2004, Pages 43-48

  Chylak, Bob ^a   Keller, Frank ^a,b   Levine, Lee ^a,b  

^a Kulicke and Soffa Industries Inc   (United States)

^b Kulicke and Soffa ^*

Author keywords

[No Author keywords available]

Indexed keywords

COPPER INTERCONNECTS; WAFER PROCESSING;

CAPILLARY FLOW; COPPER; DIELECTRIC FILMS; FRACTURE; METALLIZING; PERMITTIVITY; POLYMERS; SPIN COATING; THERMAL CONDUCTIVITY;

ELECTRONICS PACKAGING;

EID: 2042474759     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (6)

1. M. Gotuaco, P.W. Lee, L.-Q. Xia, E. Yieh, "The Case for CVD Low K" Vol. 1, Issue 1, Applied Materials Update 2002.
2. D.C. Frye, "Packaging Challenges for Advanced Low K for Flip Chip and Wire Bond," 9th Annual K&S SEMICON West Tech. Symposium, July 2002.
3. L. Levine, "The Trend Toward Copper with Low k Layers Continues," Chip Scale Review, Jan.-Feb. 2002.
4. J. Brunner, F. Keller, T. Pan, "Optimization of Wire Bonding Over Cu-Low K Pad Stack," Proc. IMAPS, November 2003.
5. V. Sundararamen, D.R. Edwards, W.E. Subido, H.R. Test, "Wire Pull on Fine Pitch Pads: An Obsolete Test for First Bond Integrity," Proc. ECTC 2000.
6. I. Singh, L. Levine, J. Brunner, "Reliability Ground Rules Change at <50μm Pitch," Proc. IEMT 2003.