Process improvement of 0.13 μm Cu/Low K (Black DiamondTM) dual damascene interconnection

Microelectronics Reliability

Volumn 45, Issue 7-8, 2005, Pages 1134-1143

  Li, H Y ^a   Su, Y J ^a   Tsang, C F ^a   Sohan, S M ^a   Bliznetsov, V ^a   Zhang, L ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; ANTIREFLECTION COATINGS; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRIC RESISTANCE; INTERCONNECTION NETWORKS; OPTIMIZATION; PHOTORESISTS; RELIABILITY; SEMICONDUCTING DIAMONDS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON CARBIDE; SILICON WAFERS;

BOTTOM-ANTI-REFLECTIVE-COATING (BARC); DUAL DAMASCENCE STRUCTURE; ELECTRICAL PERFORMANCE; PROCESS IMPROVEMENT;

MICROELECTRONICS;

EID: 20344401784     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.11.057     Document Type: Article

References (4)

1. Ashok Sinha et al. Driving Chip Manufacturing Technology through "Nano-Chip" Barriers, Leadership, p. 9-11, Foresight Oct., 2001.
2. M. Fayolle Integration of Cu/SiOC in Cu dual damascene interconnect for 0.1 μm technology Microelectron Eng 64 2002 35 42
3. C.F. Tsang Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process Microelectron J 34 2003 1051 1058
4. A.G. Sabnis VLSI Reliabilty 1990 Harcourt Brace Jovanovich Publisher Boston (Chapter 2). p. 14