Instruction set extension for long integer modulo arithmetic on RISC-based smart cards

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn 2002-January, Issue , 2002, Pages 13-19

  Grossschadl J ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Acceleration; Arithmetic; Clocks; Computer aided instruction; Computer architecture; Coprocessors; Frequency; Public key cryptography; Reduced instruction set computing; Smart cards

Indexed keywords

ACCELERATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; DIGITAL ARITHMETIC; HARDWARE SECURITY; INTEGER PROGRAMMING; JAVA PROGRAMMING LANGUAGE; PROGRAM PROCESSORS; PUBLIC KEY CRYPTOGRAPHY; REDUCED INSTRUCTION SET COMPUTING; SMART CARDS; TRANSPORTATION;

APPLICATION-SPECIFIC INSTRUCTION SET; CO-PROCESSORS; EFFICIENT IMPLEMENTATION; FREQUENCY; INSTRUCTION SET EXTENSION; MULTIAPPLICATION SMART CARDS; MULTIPLE-PRECISION MULTIPLICATIONS; PUBLIC KEY CRYPTOSYSTEMS;

COMPUTER AIDED INSTRUCTION;

EID: 20344397318     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CAHPC.2002.1180754     Document Type: Conference Paper

References (25)

1. K. Küçükçakar, "An ASIP design methodology for embedded systems," in Proceedings of the 7th International Symposium on Hardware/Software Codesign (CODES '99) , pp. 17-21, May 1999.
2. R. E. Gonzalez, "Xtensa: A configurable and extensible processor," IEEE Micro, vol. 20, no. 2, pp. 60-70, Mar./Apr. 2000.
3. M. Gschwind, "Instruction set selection for ASIP design," in Proceedings of the 7th International Symposium on Hardware/Software Codesign (CODES '99) , pp. 7-11, May 1999.
4. A. Wang et al, "Hardware/software instruction set configurability for system-on-chip processors," in Proceedings of the 38th Design Automation Conference (DAC 2001), pp. 184-188, June 2001.
5. R. B. Lee, "Multimedia extensions for general-purpose processors," in Proceedings of the 1997 IEEE Workshop on Signal Processing Systems (SiPS '97) , pp. 9-23, Nov. 1997.
6. R. B. Lee, "Accelerating multimedia with enhanced microprocessors," IEEE Micro, vol. 15, no. 2, pp. 22-32, Apr. 1995.
7. R. B. Lee and J. B. Huck, "64-bit and multimedia extensions in the PA-RISC 2.0 architecture," in Proceedings of the 41st IEEE Computer Society International Conference (COMPCON '96), pp. 152-160, Feb. 1996.
8. A. Peleg and U. Weiser, "MMX technology extension to the Intel architecture," IEEE Micro, vol. 16, no. 4, pp. 42-50, Aug. 1996.
9. J. Burke, J. McDonald, and T. M. Austin, "Architectural support for fast symmetric-key cryptography," in Proceedings of the 9th Int. Conference on Architectural Support for Programming Languages and Operating Systems (AS-PLOS 2000), pp. 178-189, Nov. 2000.
10. R. B. Lee, Z. Shi, and X. Yang, "Efficient permutation instructions for fast software cryptography," IEEE Micro, vol. 21, no. 6, pp. 56-69, Nov./Dec. 2001.
11. D. R. Stinson, Cryptography: Theory and Practice, Second Edition, Chapman & Hall/CRC, Feb. 2002.
12. R. L. Rivest, A. Shamir, and L. M. Adleman, "A method for obtaining digital signatures and public key cryptosystems," Communications of the ACM, vol. 21, no. 2, pp. 120-126, Feb. 1978.
13. J.-F. Dhem and N. Feyt, "Hardware and software symbiosis helps smart card evolution," IEEE Micro, vol. 21, no. 6, pp. 14-25, Nov./Dec. 2001.
14. ARM Limited, "ARM SecurCore Solutions," Product brief, available for download at http://www.arm.com/aboutarm/4XAFLB/$File/SecurCores.pdf, Feb. 2002.
15. J.-F. Dhem, Design of an efficient public-key cryptographic library for RISC-based smart cards, Ph.D. Thesis, Université Catholique de Louvain, Louvain-la-Neuve, Belgium, 1998.
16. The Open SystemC Initiative (OSCI), SystemC Version 2.0 User's Guide, available for download at http://www.systemc.org, Apr. 2002.
17. D. E. Knuth, Seminumerical Algorithms, vol. 2 of The Art of Computer Programming, Addison-Wesley, third edition, 1998.
18. I. Koren, Computer Arithmetic Algorithms, A. K. Peters, Ltd., 2002.
19. Ç. K. Koç, T. Acar, and B. S. Kaliski, "Analyzing and comparing Montgomery multiplication algorithms," IEEE Micro, vol. 16, no. 3, pp. 26-33, June 1996.
20. P. L. Montgomery, "Modular multiplication without trial division," Mathematics of Computation, vol. 44, no. 170, pp. 519-521, 1985.
21. MIPS Technologies, Inc., "MIPS32™ architecture for programmers, Vol. I & II," Available for download at http://www.mips.com/publications/index.html, Mar. 2001.
22. MIPS Technologies, Inc., "MIPS32 4Km™ processor core family data sheet," Available for download at http://www.mips.com/publications/index.html, Sep. 2001.
23. X. Huang, W.-J. Liu, and B. W. Wei, "A high-performance CMOS redundant binary multiplication-and-accumulation (MAC) unit," IEEE Transactions on Circuits and Systems, vol. 41, no. 1, pp. 33-39, Jan. 1994.
24. A. A. Farooqui and V. G. Oklobdžija, "General data-path organization of a MAC unit for VLSI implementation of DSP processors," in Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (ISCAS '98) , vol. 2, pp. 260-263, May 1998.
25. D. M. Gordon, "A survey of fast exponentiation methods," Journal of Algorithms, vol. 27, no. 1, pp. 129-146, Apr. 1998.