A novel design of an asymmetric D-latch

2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: Digest of Papers

Volumn , Issue , 2004, Pages 261-264

  Trotta, S ^a   Sundermeyer, J ^a   Weber, N ^a   Saurer, J ^a  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; FEEDBACK; FREQUENCIES; FREQUENCY DIVIDING CIRCUITS; LOGIC DESIGN; TOPOLOGY; WAVEFORM ANALYSIS;

CLOCK CYCLES; CLOCK SIGNALS; INPUT DATA; REGENERATIVE BLOCKS;

FLIP FLOP CIRCUITS;

EID: 20344375982     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. B. Razavi, "Design of integrated circuits for optical communications". McGraw - Hill, 2003.
2. H.-M. Rein and M. Moller, "Design consideration for very-high-speed Si-bipolar IC's operating up to 50Gb/s", IEEE J. Solid-State Circuits, Vol. 31, pp. 1076-1090, 1996.
3. AMS, Austriamicrosystems, "0.35μm HBT BICMOS Process Parameters", Document Number: ENG 219, Revision #2.0. Company Confidential.
4. K. Murata and M.Yoneyama, "A 40-Gbit/s Superdynamic Decision IC Fabricated with 0.12-μm Ga As Mesfet's", IEEE J. Solid-State Circuits, Vol. 33, pp. 1527-1535, 1998.