SVX4: A new deep submicron readout IC for the tevatron collider at fermilab

IEEE Nuclear Science Symposium Conference Record

Volumn 1, Issue , 2003, Pages 402-407

  Krieger, B ^a   Alfonsi, S ^b,c   Bacchetta, N ^c   Centreo, S ^b,c   Christofek, L ^d   Garcia Sciveres, M ^a   Haber, C ^a   Hanagaki, K ^e   Hoff, J ^e   Johnson, M ^e   Von Der Lippe, H ^a   Mandelli, E ^a   Meng, G ^b,c   Nomerotski, A ^e   Pellet, D ^f   Rapidis, P ^e   Utes, M ^e   Walder, J P ^a   Weber, M ^a   Wester, W ^e   Wilkes, T ^f   Yarema, R ^e   Yao, W ^f   Zimmerman, T ^e   more..

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^b UNIVERSITY OF PADOVA   (Italy)

^c SEZIONE DI PADOVA   (Italy)

^d UNIVERSITY OF KANSAS   (United States)

^e FERMI NATIONAL ACCELERATOR LABORATORY   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COLLIDING BEAM ACCELERATORS; ELECTRIC CHARGE; FABRICATION; SIGNAL PROCESSING; SILICON; SPURIOUS SIGNAL NOISE; TOPOLOGY; TRANSCEIVERS;

CDF; HYBRID CIRCUIT BOARDS; RADIATION TOLERANCE; SEU TOLERANCE;

INTEGRATED CIRCUITS;

EID: 19944428929     PISSN: 10957863     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/nssmic.2003.1352072     Document Type: Conference Paper

References (10)

1. G. Chiarelli, "Higgs discovery before LHC?," FERMILAB-CONF-01/092-E.
2. M. Garcia-Sciveres, et at., "The SVX3D integrated circuit for dead-timeless silicon strip readout," Nucl. Instr. Meth. A, vol. 435, pp. 58-64, Oct. 1999.
3. T. Zimmerman, et al., "A deadtimeless readout chip for silicon strip detectors," Nucl. Instr. Meth. A, vol. 409, pp. 369-374, May 1998.
4. L. Blanquart, et al., "FEI-2: A front-end readout chip designed in a commercial 0.25 μm process for the ATLAS pixel detector at LHC," presented at the IEEE Nuclear Science Symposium, Portland, Oregon, October 2003, (to be published).
5. G. Anelli, et al., "Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects," IEEE Trans. Nucl. Sci., vol. 46, pp. 1690-1696, Dec. 1999.
6. T. Calin, M. Nicolaidis, R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878. Dec. 1996.
7. HSPICE is a Synopsys Corp. EDA simulation tool.
8. Nanosim is a Synopsys Corp. EDA simulation tool.
9. Calibre is a Mentor Graphics Corp. EDA IC verification tool.
10. Diva LVS is a Cadence Design Systems EDA IC verification tool.