High performance adder cell for low power pipelined multiplier

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 57-60

  Wu, Angus ^a  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; LOGIC CIRCUITS; LOGIC DESIGN; MULTIPLYING CIRCUITS; PERFORMANCE; PIPELINE PROCESSING SYSTEMS;

ADDER CELL; COMPLEMENTARY PASS TRANSISTOR LOGIC; DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC;

ADDERS;

EID: 0029716111     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)