Effect of nanotopography in direct wafer bonding: Modeling and measurements

IEEE Transactions on Semiconductor Manufacturing

Volumn 18, Issue 2, 2005, Pages 289-296

  Turner, K T ^a   Spearing, S M ^a,b   Baylies, W A ^c   Robinson, M ^d   Smythe, R ^d  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^c Bay Tech Group   (United States)

^d ZYGO CORPORATION   (United States)

Author keywords

Direct bonding; Microelectromechanical systems (MEMS); Nanotopography; Silicon on insulator (SOI); Wafer bonding

Indexed keywords

BONDING; INTERFACIAL ENERGY; MICROELECTROMECHANICAL DEVICES; NANOTECHNOLOGY; POLISHING; ROUGHNESS MEASUREMENT; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; STRAIN;

DIRECT BONDING; NANOTOPOGRAPHY; ROUGHNESS TOLERANCES; WAFER BONDING;

SILICON WAFERS;

EID: 19544383077     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2005.845009     Document Type: Conference Paper

References (24)

1. SEMI, "SEMI M43-0301: Guide for reporting wafer nanotopography, " Semiconductor Equipment and Materials International, 2001.
2. N. Miki and S. Spearing, "Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers," J. Appl. Phys., vol. 94, no. 10, pp. 6800-6806, 2003.
3. R. Stengl, K. Mitani, V. Lehmann, and U. Gosele, "Silicon wafer bonding: chemistry, elasto-mechanics, and manufacturing," in Proc. 1989 IEEE SOS/SOI Technology Conf., p. 123.
4. Q.-Y. Tong and U. Gösele, "Thickness considerations in direct silicon wafer bonding," J. Electrochem. Soc., vol. 142, no. 11, pp. 3975-3979, 1995.
5. H. Yu and Z. Suo, "A model of wafer bonding by elastic accommodation," J. Mech. Phys. Solids, vol. 46, no. 5, pp. 829-844, 1998.
6. K. Turner and S. Spearing, "Modeling of direct wafer bonding: Effect of wafer bow and etch patterns," J. Appl. Phys., vol. 92, no. 12, pp. 7658-7666, 2002.
7. K. Turner, M. Thouless, and S. Spearing, "Mechanics of wafer bonding: Effect of wafer bow and etch patterns," J. Appl. Phys., vol. 95, no. 1, pp. 349-355, 2004.
8. K. Ravi, "Wafer flatness requirements for future technologies," Future Fab Int., vol. 7, pp. 207-212, 2000.
9. D. Boning and B. Lee, "Nanotopography issues in shallow trench isolation CMP," MRS Bull., vol. 27, no. 10, pp. 761-765, 2002.
10. B. Lee, D. Boning, W. Baylies, N. Poduje, P. Hester, H. Xia, J. Valley, C. Koliopoulus, D. Hetherington, H. Sun, and M. Lacey, "Wafer nanotopography effects on CMP: experimental validation of modeling methods," in Proc. Materials Research Society Symp., vol. 671, 2001, pp. M4.9.1-M4.9.6.
11. B. Lee, T. Gan, D. Boning, P. Hester, N. Poduje, and W. Baylies, "Nanotopography effects on chemical mechanical polishing for shallow trench isolation," in Proc. IEEE Int. Symp. Semiconductor Manufacturing Conf., 2000, pp. 425-432.
12. T. Katoh, J.-G. Park, W.-M. Lee, H. Jeon, U.-G. Paik, and H. Suga, "The nanotopography effect of improved single-side polished wafer on oxide chemical mechanical polishing," Jpn. J. Appl. Phys. 2, Lett., vol. 41, pp. L443-L446, 2002.
13. J.-G. Park, T. Katoh, H.-C. Yoo, and J.-H. Park, "Spectral analyses of the impact of nanotopography of silicon wafers on oxide chemical mechanical polishing," Jpn. J. Appl. Phys. 2, Lett., vol. 40, pp. L857-L860, 2001.
14. J.-G. Park, T. Katoh, H.-C. Yoo, D.-H. Lee, and U.-G. Paik, "Spectral analyses on pad dependency of nanotopography impact on oxide chemical mechanical polishing," Jpn. J. Appl. Phys. 2, Lett., vol. 41, pp. L17-L19, 2002.
15. B. Lee, D. Boning, W. Baylies, N. Poduje, and J. Valley, "Modeling and mapping of nanotopography interactions with CMP," in Proc. Materials Research Soc. Symp., vol. 732E, 2002, pp. I1.1.1-I1.1.12.
16. G. Wenski, T. Altmann, W. Winkler, G. Heier, and G. Holker, "Doubleside polishing - a technology for 300 mm wafer manufacturing," Mater. Sci. Semicond. Process., vol. 5, pp. 375-380, 2003.
17. MEMC, Application Note: AE-008, Aug. 2001.
18. J. Valley, C. Koliopoulos, and S. Tang, "Interferometric metrology of wafer nanotopography for advanced CMOS process integration," Proc. SPIE-Int. Soc. Opt. Eng., vol. 4449, pp. 160-168, 2001.
19. R. Schmolke, R. Deters, P. Thieme, R. Pech, H. Schwenk, and G. Diakourakis, "On the impact of nanotopography of silicon wafers on post-cmp oxide layers," J. Electrochem. Soc., vol. 149, no. 4, pp. G257-G265, 2002.
20. T. Raymond, D. Neal, D. Topa, and T. Schmitz, "High-speed noninterferometric nanotopographic characterization of Si wafer surfaces," Proc. SPIE-Int. Soc. Opt. Eng., vol. 4809, pp. 208-216, 2002.
21. Q.-Y. Tong and U. Gosele, Semiconductor Wafer Bonding: Science and Technology. New York: Wiley, 1999.
22. VeriFire AT Interferometer System Operating Manual OMP-0480, Zygo Corp., Middlefield, CT, 2002.
23. F. Reidel, H.-A. Gerber, and P. Wagner, "Impact of filtering on nanotopography measurement of 300 mm silicon wafers," Mater. Sci. Semicond. Process., vol. 5, pp. 465-472, 2003.
24. "ASTM F1811-97: Standard practice for estimating the power spectral density function and related finish parameters from surface profile data," ASTM Int., 1997.