Nanotopography issues in shallow trench isolation CMP

MRS Bulletin

Volumn 27, Issue 10, 2002, Pages

  Boning, Duane ^a   Lee, Brian ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Chemical mechanical planarization; Chemical mechanical polishing; CMP; Contact wear simulation; Nanotopography; Shallow trench isolation (STI); Silicon wafers

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COMPUTER SIMULATION; EROSION; FAILURE (MECHANICAL); INTEGRATED CIRCUITS; SILICON WAFERS;

SHALLOW TRENCH ISOLATION (STI);

NANOTECHNOLOGY;

EID: 0036802639     PISSN: 08837694     EISSN: None     Source Type: Journal    
DOI: 10.1557/mrs2002.246     Document Type: Article

References (13)

1. K.V. Ravi, Future Fab Int. 7 (1999) p. 207.
2. C.S. Xu, E. Zhao, R. Jairath, and W. Krussell, Electrochem. Solid-State Lett. 1 (4) (1998) p. 181.
3. B. Lee, D.S. Boning, W. Baylies, N. Poduje, P. Hester, Y. Xia, J. Valley, C. Koliopoulos, D. Hetherington, H. Sun, and M. Lacy, in Chemical-Mechanical Polishing 2001-Advances and Future Challenges, edited by S.V. Babu, K.C. Cadien, and H. Yano (Mater. Res. Soc. Symp. Proc. 671, Warrendale, PA, 2001) p. M4.9.1.
4. J.-G. Park, T. Katoh, H.C. Yoo, and J.-H. Park, Jpn. J. Appl. Phys., Part 2: Lett. 40 (2001) p. L857.
5. R. Schmolke, R. Deters, P. Thieme, R. Pech, H. Schwenk, and G. Diakourakis, J. Electrochem. Soc. 149 (4) (2002) p. G257.
6. B. Lee, D.S. Boning, W. Baylies, N. Poduje, and J. Valley, "Modeling and Mapping of Nanotopography Interactions with CMP," presented at Symposium I, Materials Research Society Meeting, San Francisco, April 2002, paper No. I1.5.
7. O.G. Chekina and L.M. Keer, J. Electrochem. Soc. 145 (6) (1998) p. 2100.
8. T. Yoshida, in Proc. 3rd Int. Symp. on Chemical-Mechanical Planarization in IC Device Manufacturing, Vol. 99-37 (The Electrochemical Society, Pennington, NJ, 1999) p. 593.
9. D. Ouma, D. Boning, J. Chung, G. Shinn, L. Olsen, and J. Clark, in Proc. Int. Interconnect Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 1998) p. 67.
10. D. Boning, B. Lee, W. Baylies, N. Poduje, and J. Valley, "Impact of Nanotopography on STI CMP in Future Technologies," presented at the Workshop on Metrology for Silicon Wafers for 100-nm Technology Generations and Beyond, SEMI/Europa, Munich, April 2002.
11. D.P. Shum, J.M. Higman, M.G. Khazhinsky, K.Y. Wu, S. Kao, J.D. Burnett, and C.T. Swift, in IEDM Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 1997) p. 665.
12. J.T. Pan, D. Ouma, P. Li, D. Boning, F. Redecker, J. Chung, and J. Whitby, "Planarization and Integration of Shallow Trench Isolation," presented at the VLSI Multilevel Interconnect Conf., Santa Clara, CA, June 1998.
13. B. Lee, PhD thesis, Massachusetts Institute of Technology, May 2002.