A simple mechanism for detecting ineffectual instructions in slipstream processors

IEEE Transactions on Computers

Volumn 53, Issue 4, 2004, Pages 399-413

  Koppanalil, Jinson J ^a   Rotenberg, Eric ^b  

^a ARM Inc   (United States)

^b North Carolina State University   (United States)

Author keywords

Chip multiprocessor; Microarchitecture; Multithreading; Preexecution; Slipstream

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER HARDWARE; DATA PROCESSING; INFORMATION RETRIEVAL SYSTEMS; MICROPROCESSOR CHIPS; STORAGE ALLOCATION (COMPUTER);

CHIP MULTIPROCESSOR; INEFFECTUAL INSTRUCTIONS; MICROARCHITECTURE; MULTITHREADING; PREEXECUTION; SLIPSTREAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 1942500431     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.1268397     Document Type: Article

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