Models of computation and languages for embedded system design

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 2, 2005, Pages 114-129

  Jantsch, A ^a   Sander, I ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; SEMANTICS;

COORDINATION LANGUAGES; MODELS OF COMPUTATION (MOC); SOFTWARE INTERFACE SPECIFICATION; SYSTEM ON CHIP (SOC);

EMBEDDED SYSTEMS;

EID: 19344368232     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045098     Document Type: Conference Paper

References (78)

1. Edwards, S., Lavagno, L., Lee, E.A., and Sangiovanni-Vincentelli, A.: 'Design of embedded systems: formal models, validation, and synthesis', Proc. IEEE, 1997, 85, (3), pp. 366-390
2. Keutzer, K., Malik, S., Newton, A.R., Rabaey, J.M., and Sangiovanni-Vincentelli, A.: 'System-level design: orthogonolization of concerns and platform-based design', IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000, 19, (12), pp. 1523-1543
3. Benveniste, A., and Berry, G.: 'The synchronous approach to reactive and real-time systems', Proc. IEEE, 1991, 79, (9), pp. 1270-1282
4. Grötker, T., Liao, S., Martin, G., and Swan, S.: 'System design with systemC' (Kluwer Academic Publishers, 2002)
5. Schaumont, P., Vernalde, S., Rijnders, L., Engels, M., and Bolsens, I.: 'A programming environment for the design of complex high speed ASICs'. Proc. Design Automation Conf., Anaheim, CA, USA, 1997
6. Clarke, E.M., and Wing, J.M.: 'Formal methods: state of the art and future directions', ACM Comput. Surv., 1996, 28, (4)
7. Kern, C., and Greenstreet, M.R.: 'Formal verification in hardware design: A survey', ACM Trans. Des. Autom. Electron. Syst., 1999, 4, (2)
8. McFarland, M.C.: 'Formal verification of sequential hardware: a tutorial', IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993, 12, (5), pp. 633-654
9. Jantsch, A., and Sander, I.: 'On the roles of functions and objects in system specification'. Proc. Int. Workshop on Hardware/Software Codesign, 2000
10. Jantsch, A.: 'Models of embedded computation', in 'Embedded systems' (CRC Press, 2004)
11. Lee, E.A., and Sangiovanni-Vincentelli, A.: 'A framework for comparing model of computation', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1998, 17, (12), pp. 1217-1229
12. Paul, J.M., and Thomas, D.E.: 'Models of computation for systems-on-chip', in Jerraya, A., and Wolf, W. (Eds.): 'Multiprocessor systems-on-chip' (Morgan Kaufman Publishers, 2004), Chap. 15
13. Savage, J.E.: 'Models of computation, exploring the power of computing' (Addison Wesley, 1998)
14. Taylor, R.G.: 'Models of computation and formal language' (Oxford University Press, New York, 1998)
15. Eker, J., Janneck, J.W., Lee, E.A., Liu, J., Liu, X., Ludvig, J., Neuendorffer, S., Sachs, S., and Xiong, Y.: 'Taming heterogeneity - the Ptolemy approach', Proc. IEEE, 2003, 91, (1), pp. 127-144
16. Jantsch, A.: 'Modeling embedded systems and SoCs - concurrency and time in models of computation: Systems on silicon' (Morgan Kaufmann Publishers, June 2003)
17. Sander, I., and Jantsch, A.: 'System modeling and transformational design refinement in ForSyDe', IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004, 23, (1), pp. 17-32
18. Jones, S.P.: 'Haskell 98 language and libraries' (Cambridge University Press, 2003)
19. Mathaikutty, D., Patel, H., and Shukla, S.: 'A functional programming framework of heterogeneous model of computations for system design'. Proc. Forum on Specification and Design Languages, Lille, France, September 2004
20. Patel, H.D., and Shukla, S.K.: 'SystemC kernel extensions for heterogeneous system modelling' (Kluwer Academic Publishers, Boston/Dordrecht/London, 2004)
21. Skillicorn, D.B., and Talia, D.: 'Models and languages for parallel computation', ACM Comput. Surv., 1998, 30, (2), pp. 123-169
22. Flynn, M.J.: 'Some computer organisations and their effectiveness', IEEE Trans. Comput., 1972, C-21, (9), pp. 948-960
23. Dabney, J., and Harman, T.L.: 'Mastering SIMULINK 2' (Prentice Hall, 1998)
24. Elmqvist, H., Mattsson, S.E., and Otter, M.: 'Modelica - the new object-oriented modeling language'. Proc. 12th European Simulation Multiconference, June 1998
25. Cassandras, C.G.: 'Discrete event systems: modeling and performance analysis' (Asken Associates, 1993)
26. IEEE, IEEE Standard VHDL Language Reference Manual. IEEE, 2002
27. IEEE, IEEE Standard for Verilog Hardware Description Language. IEEE, 2001
28. Halbwachs, N., Caspi, P., Raymond, P., and Pilaud, D.: 'The synchronous data flow programming language LUSTRE', Proc. IEEE, 1991, 79, (9), pp. 1305-1320
29. Winskel, G.: 'The formal semantics of programming languages' (MIT Press, 1993)
30. Berry, G.: 'The constructive semantics of pure Esterel - draft version 3'. Technical report, INRIA, 06902 Sophia-Antipolis CDX, France, 2 July 1999
31. Le Guernic, P., Gautier, T., Le Borgne, M., and Le Marie, C.: 'Programming real-time applications with SIGNAL', Proc. IEEE, 1991, 79, (9), pp. 1321-1335
32. Lee, E.A., and Parks, T.M.: 'Dataflow process networks', Proc. IEEE, 1995, 83, (5), pp. 773-799
33. Kahn, G.: 'The semantics of a simple language for parallel programming'. Proc. IFIP Congress 74, Stockholm, Sweden, North-Holland, 1974
34. Kahn, G., and MacQueen, D.B.: 'Coroutines and networks of parallel processes', IFIP'77 (North-Holland, 1977)
35. Lee, E.A., and Messerschmitt, D.G.: 'Static scheduling of synchronous data flow programs for digital signal processing', IEEE Trans. Comput., 1987, C-36, (1), pp. 24-35
36. Lee, E.A., and Messerschmitt, D.G.: 'Synchronous data flow', Proc. IEEE, 1987, 75, (9), pp. 1235-1245
37. Hoare, C.A.R.: 'Communicating sequential processes', Commun. ACM, 1978, 21, (8), pp. 666-676
38. Milner, R.: 'A calculus of communicating systems', Lect. Notes Comput. Sci., 1980, 92
39. Milner, R.: 'Communication and concurrency' (Prentice Hall, 1989)
40. Booch, G., and Bryan, D.: 'Software engineering with Ada' (The Benjamin/Cummings Publishing Company, 1994)
41. Girault, A., Lee, B., and Lee, E.A.: 'Hierarchical finite state machines with multiple concurrency models', IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999, 18, (6), pp. 742-760
42. Jantsch, A., and Bjuréus, P.: 'Composite signal flow: a computational model combining events, sampled streams, and vectors'. Proc. Design and Test Europe, Conf. (DATE), Paris, France, March 2000, pp. 154-160
43. Bjuréus, P., and Jantsch, A.: 'Modeling of mixed control and dataflow systems in MASCOT', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2001, 9, (5), pp. 690-704
44. Ziegenbein, D., Richter, K., Ernst, R., Thiele, L., and Teich, J.: 'SPI - a System model for heterogeneously specified embedded systems', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2002, 10, (4), pp. 379-389
45. Strehl, K., Thiele, L., Gries, M., Ziegenbein, D., Ernst, R., and Teich, J.: 'FunState - an internal design representation for codesign', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2001, 9, (4), pp. 524-544
46. Rose, F., Leiserson, C., and Saxe, J.: 'Optimizing synthesis circuitry by retiming'. Proc. Caltech Conf. on VLSI, 1983, pp. 41-67
47. Wehn, N., Biesenack, J., Langmaier, T., Muench, M., Pilsl, M., Rumler, S., and Duzy, P.: 'Scheduling of behavioural VHDL by retiming techniques'. Proc. EuroDAC 94, 1994 pp. 546-551
48. Ashenden, P.J., Peterson, G.D., and Teegarden, D.A.: 'Designers guide to VHDL-AMS' (Morgan Kaufman, 2002)
49. Synopsys Inc.: CoCentric(R) SystemC compiler behavioral modeling guide, 2002
50. Synopsys Inc.: CoCentric(R) SystemC compiler RTL user and modeling guide, 2002
51. Vachoux, A., Grimm, C., Einwich, K.: 'SystemC-AMS requirements, design objectives and rationale'. Proc. Design Automation and Test Europe Conf., 2003
52. Benveniste, A., Caspi, P., Edwards, S.A., Halbwachs, N., Le Guernic, P., and Simone, R.D.: 'The synchronous languages 12 years later', Proc. IEEE, 2003, 91, (1), pp. 64-83
53. Halbwachs, N.: 'Synchronous programming of reactive systems' (Kluwer Academic Publishers, 1993)
54. Berry, G.: The foundations of Esterel', in Plotkin, G., Stirling, C., and Tofte, M. (Eds.): 'Proof, language and interaction: essays in honour of Robin Milner' (MIT Press, 1998)
55. Berry, G., and Gonthier, G.: 'The Esterel synchronous programming language: design, semantics, implementation', Science Comput. Program., 1992, 19, (2), pp. 87-152
56. Boussinot, F., and De Simone, R.: 'The ESTEREL language', Proc. IEEE, 1991, 79, (9), pp. 1293-1304
57. Berry, G.: 'The Esterel v5 language primer'. Ecole des Mines and INRIA, 06565 Sophia-Antipolis, France, version v5_91 edition, July 2000
58. Harel, D.: 'Statecharts: a visual formalism for complex systems', Sci. Comput. Program., 1987, 8, (3), pp. 231-274
59. Maraninchi, F.: 'The Argos language: graphical representation of automata and description of reactive systems'. IEEE Workshop on Visual Languages, October 1991
60. Berry, G.: 'A hardware implementation of pure Esterel'. Proc. Int. Workshop on Formal Methods in VLSI Design, January 1991
61. Rocheteau, F., and Halbwachs, N.: 'Implementing reactive programs on circuits: a hardware implementation of lustre'. REX Workshop Proc., June 1992
62. Halbwachs, N., and Raymond, P.: 'Validation of synchronous reactive systems: from formal verification to automatic testing'. Proc. ASIAN'99, Asian Computing Science Conf., Lect. Notes Comput. Sci., Vol. 1742, 12, Phuket, Thailand, December 1999, pp. 1-12.
63. Dennis, J.B.: 'First version of a data flow procedure language', Lect. Notes Comput. Sci., 1974, 19, pp. 362-376
64. Ashcroft, E., and Wadge, W.: 'Lucid, a nonprocedural language with iteration', Commun. ACM, 1977, 20, (7), pp. 519-526
65. Bilsen, G., Engels, M., Lauwereins, R., and Peperstraete, J.A.: 'Cyclo-static data flow'. Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, 1995 pp. 3255-3258
66. Buck, J.T.: 'Scheduling dynamic dataflow graphs with bounded memory using the token flow model'. PhD thesis, Department of Electrical Engineering and Computer Science, University of California at Berkeley, USA, 1993
67. Faustini, A.A., Jagganathan, R., Ashcroft, E.A., and Wadge, W.W.: 'Multidimensional programming' (Oxford University Press, 1995)
68. Wadge, W., and Ashcroft, E.: 'Lucid, the dataflow programming language' (Academic Press, 1985)
69. Jagannathan, R.: 'Coarse-grain dataflow programming of conventional parallel computers', in Bic, L., Gaudiot, J.-L., and Gao, G. (Eds.): 'Advanced in dataflow computing and multithreading' (IEEE Computer Society Press, 1995), pp. 113-129
70. Hylands, C., Lee, E.A., Liu, J., Liu, X., Neuendorffer, S., Xiong, Y., and Zheng, H. (Eds): 'Ptolemy II - heterogeneous concurrent modeling and design in Java', volume 2, Department of Electrical Engineering and Computer Sciences University of California at Berkeley, USA, 2003. Memorandum UCB/ERL M03/29, version 3.0
71. Celoxica Limited. : Handel-C language reference manual, dk2.0 edition, 2003. RM-1003-4.0
72. Lee, E.A.: Overview of the ptolemy project. Technical Report UCB/ERL M03/25, University of California, Berkeley, CA, USA, July 2003
73. Lee, E.A., and Xiong, Y.: 'A behavioral type system and its application in Ptolemy II', Form. Asp. Comput., 2004, 16, pp. 210-237
74. ITRS Technology Working Group.: International Technology Roadmap for Semiconductors - design, 2003, edition, 2003
75. Habibi, A., and Tahar, S.: 'A survey: system-on-a-chip design and verification'. Technical report, Electrical and Computer Engineering Department, Concordia University, Montreal, Canada 2003
76. Roy, S.K., Ramesh, S., Chakraborty, S., Nakata, T., and Rajan, S.P.: 'Functional verification of system on chips practices, issues and challenges'. Proc. 15th Int. Conf. on VLSI Design, 2002
77. Jäger, S.: Technical and economical barriers and drivers for the introduction of formal methods in the verification of digital systems'. Master's thesis, Darmstadt University of Technology, Department of Electrical Engineering and Information Technology, Germany, January 2004
78. Lemire, J.-F., Regimbai, S., Bois, S., Savaria, Y., and Aboulhamid, E.M.: 'A survey on current functional verification practice'. Technical report, École Polytechniqué de Montréal, Université de Montréal, Canada, 2002