FunState - An internal design representation for codesign

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 4, 2001, Pages 524-544

  Strehl, Karsten ^a,b   Thiele, Lothar ^a,c   Gries, Matthias ^a,c   Ziegenbein, Dirk ^a,d   Ernst, Rolf ^a,d   Teich, Jürgen ^a,e  

^a IEEE   (Germany)

^b Etas GmbH   (Germany)

^c ETH ZURICH   (Switzerland)

^d TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

^e Lehrstuhl für Konstruktions und Antriebstechnik KAt   (Germany)

Author keywords

Formal verification; High level synthesis; Internal specification model; Model of computation; Symbolic scheduling

Indexed keywords

INTERNAL SPECIFICATION; SYMBOLIC SCHEDULING;

ASYNCHRONOUS TRANSFER MODE; BOOLEAN ALGEBRA; COMPUTATIONAL COMPLEXITY; COMPUTER SYSTEMS PROGRAMMING; CONSTRAINT THEORY; DATA FLOW ANALYSIS; MATHEMATICAL MODELS; PETRI NETS; QUEUEING THEORY;

EMBEDDED SYSTEMS;

EID: 0035426076     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.931229     Document Type: Article

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