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Volumn , Issue , 2004, Pages 77-82

TCAD tools for efficient 3D simulations of geometry effects in floating-gate structures

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; GEOMETRY; MULTILAYERS; OPTIMIZATION; POLYSILICON; PROBLEM SOLVING;

EID: 18844397014     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (12)
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    • New method for extraction of the coupling ratios in FLOTOX EEPROMS cells
    • B. Moison et al., "New Method for Extraction of the Coupling Ratios in FLOTOX EEPROMS Cells," IEEE Trans. Electron Devices, vol. 40, pp. 1870-1872, 1993.
    • (1993) IEEE Trans. Electron Devices , vol.40 , pp. 1870-1872
    • Moison, B.1
  • 3
    • 0029273480 scopus 로고
    • A simple method for determining capacitive coupling coefficients in floating-gate devices
    • Woong L. Choi et al., "A Simple Method for Determining Capacitive Coupling Coefficients in Floating-Gate Devices," Solid-State Electronics, vol. 38, pp. 581-586, 1995.
    • (1995) Solid-state Electronics , vol.38 , pp. 581-586
    • Choi, W.L.1
  • 4
    • 0029778572 scopus 로고    scopus 로고
    • Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices
    • S. Mori et al., "Thickness Scaling Limitation Factors of ONO Interpoly Dielectric for Nonvolatile Memory Devices," IEEE Trans. Electron Devices, vol. 43, pp. 47-53, 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , pp. 47-53
    • Mori, S.1
  • 5
    • 0028590423 scopus 로고
    • Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction
    • H. Watanabe et al., "Scaling of Tunnel Oxide Thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction," in VLSI Symp. Dig. Tech. Papers, pp. 47-48, 1994.
    • (1994) VLSI Symp. Dig. Tech. Papers , pp. 47-48
    • Watanabe, H.1
  • 6
    • 0026105473 scopus 로고
    • Polyoxide thinning limitation and superior ONO interpoly dielectric for nonvolatile memory devices
    • S. Mori et al., "Polyoxide Thinning Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory Devices," IEEE Trans. Electron Devices, vol. 38, pp. 270-277, 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 270-277
    • Mori, S.1
  • 8
    • 0032687955 scopus 로고    scopus 로고
    • Three-dimensional modeling of the erasing operation in a submicron flash-EEPROM memory cell
    • M. Lorrenzini et al., "Three-Dimensional Modeling of the Erasing Operation in a Submicron Flash-EEPROM Memory Cell," IEEE Trans. Electron Devices, vol.46, pp. 975-983, 1999.
    • (1999) IEEE Trans. Electron Devices , vol.46 , pp. 975-983
    • Lorrenzini, M.1
  • 9
    • 18844427216 scopus 로고    scopus 로고
    • ISE Integrated Systems Engineering AG, Zurich, Switzerland
    • NOFFSET3D User Manual, Release 9.5, ISE Integrated Systems Engineering AG, Zurich, Switzerland, 2003.
    • (2003) NOFFSET3D User Manual, Release 9.5
  • 10
    • 10944271036 scopus 로고    scopus 로고
    • ISE Integrated Systems Engineering AG, Zurich, Switzerland
    • DESSIS User Manual, Release 9.5, ISE Integrated Systems Engineering AG, Zurich, Switzerland, 2003.
    • (2003) DESSIS User Manual, Release 9.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.