High performance InP/InGaAs/InP DHBTs with patterned sub-collector fabricated by elevated temperature N+ implant

Solid-State Electronics

Volumn 49, Issue 6, 2005, Pages 981-985

  Chen, Mary ^a   Sokolich, Marko ^a   Chow, David ^a   Shi, Bin ^a   Rajavel, Rajesh ^a   Bui, Steven ^a   Royter, Yakov ^a   Thomas III, Steve ^a   Fields, Charles ^a  

^a Hughes Aircraft Co   (United States)

Author keywords

HBT; InP; Ion implantation; Over growth

Indexed keywords

ANNEALING; CRYSTALLINE MATERIALS; ELECTRIC CHARGE; FABRICATION; INTERFACES (MATERIALS); ION IMPLANTATION; MOLECULAR BEAM EPITAXY; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; X RAY DIFFRACTION ANALYSIS;

INP; INTERFACIAL CHARGE; OVER GROWTH; ROOM TEMPERATURE;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 18844381128     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.03.013     Document Type: Article

References (3)

1. Sokolich M, Chen MY, Chow DH, Royter Y, Thomas III S, Fields CH, et al. InP HBT integrated circuit technology with selectively implanted subcollector and regrown layers. In: GaAs IC Symp 2003. p. 219-22
2. M. Chen, M. Sokolich, D. Chow, S. Bui, Y. Royter, and S. Thomas III Patterned n+ implant into InP substrate for HBT sub-collector IEEE Trans Electron Devices 51 10 2004 1736 1739
3. M. Gauneau, R. Chaplain, A. Rupert, E.V.K. Rao, and N. Duhamel Further evidence of chromium, manganese, iron, and zinc redistribution in indium phosphide after annealing J Appl Phys 57 4 1985 1029 1035