A third-order ∑Δ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 918-925

  Shim, Jae Hoon ^a   Park, In Cheol ^b   Kim, Beomsup ^c  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Berkana Wireless   (United States)

Author keywords

Analog digital conversion; Calibration; Sigmadelta modulation

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; MODULATORS; POWER SUPPLY CIRCUITS; SILICON; SPURIOUS SIGNAL NOISE;

CALIBRATION SIGMA-DELTA MODULATION; DIGITAL-TO-ANALOG CONVERTERS; OVERSAMPLING RATIO (OSR); QUANTIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 18744377560     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845558     Document Type: Conference Paper

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