Design methodology of a configurable system-on-chip architecture

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Volumn , Issue , 2004, Pages 283-284

  Wallner, Sebastian ^a  

^a HAMBURG UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE COMPOSITION; INSTRUCTION SET ARCHITECHTURES (ISA); PARALLELISM; SYSTEM-ON-CHIP (SOC);

CODES (SYMBOLS); CONTROL THEORY; DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SIGNAL PROCESSING; SYSTEMS ANALYSIS;

COMPUTER ARCHITECTURE;

EID: 18644366560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2004.27     Document Type: Conference Paper

References (3)

1. R. Hartenstein, "A Decade of Reconfigurable Computing: a Visionary Retrospective", Int. Conf. on Design, Automation and Test in Europe (DATE 01), Munich, Germany, Mar. 12-15 2001, pp. 642-649
2. S. Wallner, von der Heide, K., "A Universal Processor for High Speed Communication", Proc. of the Int. Conf. on Communications in Computing (CIC'2001), Las Vegas, USA, Jun. 25-28 2001, CSREA Press, Vol. 1 pp. 86-92
3. S. Wallner, "A Reconfigurable Multi-threaded Architecture Model", Eighth Asia-Pacific Computer Systems Architecture Conference (ACSAC'2003), Fukushima, Japan, Springer LNCS 2823, Sep. 23-26 2003, pp. 193-207